Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1881668

1

T2

96

T3

58

T5

161823

full_word

1184038

1

T2

11

T3

7

T5

100207

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3065416	1			T2	107		T3	65		T5	262030
auto[TlIntgErrCmd]	95	1			T47	3		T48	7		T49	2
auto[TlIntgErrData]	100	1			T47	3		T48	7		T49	6
auto[TlIntgErrBoth]	95	1			T47	4		T48	6		T49	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

496631

1

T2

107

T3

65

T5

40814

auto[1]

2569075

1

T5

221216

T6

108244

T11

282666

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	216034	1			T2	96		T3	58		T5	17211
auto[TlIntgErrNone]	partial	auto[1]	1665367	1			T5	144612		T6	70530		T11	182697
auto[TlIntgErrNone]	full_word	auto[0]	280460	1			T2	11		T3	7		T5	23603
auto[TlIntgErrNone]	full_word	auto[1]	903555	1			T5	76604		T6	37714		T11	99969
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T47	2		T48	5		T49	1
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T47	1		T48	2		T49	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T109	1		T112	1		T113	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T110	1		T116	1		T117	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T47	2		T48	4		T49	3
auto[TlIntgErrData]	partial	auto[1]	44	1			T47	1		T48	2		T49	3
auto[TlIntgErrData]	full_word	auto[0]	2	1			T112	1		T117	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	6	1			T48	1		T109	1		T113	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T47	3		T48	3		T49	1
auto[TlIntgErrBoth]	partial	auto[1]	45	1			T47	1		T48	3		T109	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T49	1		T116	2		T118	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T115	1		T111	1		T116	1