Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

832938

1

T1

83

T3

266190

T6

164

full_word

521940

1

T1

9

T3

169305

T6

23

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1354588	1			T1	92		T3	435495		T6	187
auto[TlIntgErrCmd]	84	1			T50	6		T53	3		T54	5
auto[TlIntgErrData]	96	1			T50	8		T53	1		T54	8
auto[TlIntgErrBoth]	110	1			T50	6		T53	6		T54	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

230418

1

T1

92

T3

66761

T6

187

auto[1]

1124460

1

T3

368734

T11

23770

T12

77137

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	105807	1			T1	83		T3	27320		T6	164
auto[TlIntgErrNone]	partial	auto[1]	726870	1			T3	238870		T11	15484		T12	50756
auto[TlIntgErrNone]	full_word	auto[0]	124494	1			T1	9		T3	39441		T6	23
auto[TlIntgErrNone]	full_word	auto[1]	397417	1			T3	129864		T11	8286		T12	26381
auto[TlIntgErrCmd]	partial	auto[0]	27	1			T50	2		T54	1		T107	2
auto[TlIntgErrCmd]	partial	auto[1]	42	1			T50	3		T53	2		T54	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T54	1		T106	1		T113	2
auto[TlIntgErrCmd]	full_word	auto[1]	11	1			T50	1		T53	1		T107	2
auto[TlIntgErrData]	partial	auto[0]	42	1			T50	3		T53	1		T54	3
auto[TlIntgErrData]	partial	auto[1]	46	1			T50	5		T54	4		T106	2
auto[TlIntgErrData]	full_word	auto[0]	1	1			T114	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	7	1			T54	1		T107	1		T115	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T50	2		T53	2		T54	4
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T50	3		T53	4		T54	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T113	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T50	1		T54	1		T115	1