---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FpvSecCmReqFifoRptrCheck_A	0	0	290173232	0	0	0
tb.dut.FpvSecCmReqFifoWptrCheck_A	0	0	290173232	0	0	0
tb.dut.FpvSecCmRspFifoRptrCheck_A	0	0	290173232	0	0	0
tb.dut.FpvSecCmRspFifoWptrCheck_A	0	0	290173232	0	0	0
tb.dut.FpvSecCmSramReqFifoRptrCheck_A	0	0	290173232	0	0	0
tb.dut.FpvSecCmSramReqFifoWptrCheck_A	0	0	290173232	0	0	0
tb.dut.KeymgrValidChk_A	0	0	290173232	0	0	314
tb.dut.PwrmgrDataChk_A	0	0	290173232	0	0	314
tb.dut.gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A	0	0	290173232	0	0	0
tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.SecCmCFILinear_A	0	0	290173232	0	0	1254
tb.dut.gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A	0	0	290173232	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AlertTxOKnown_A	0	0	290173232	289998595	0	0
tb.dut.BusRomIndicesMatch_A	0	0	290153792	289986436	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	290173232	80	0	0
tb.dut.KeymgrDataODataKnown_A	0	0	290173232	42929623	0	0
tb.dut.KeymgrDataODataKnown_AKnownEnable	0	0	290173232	289998595	0	0
tb.dut.KeymgrDataOValidKnown_A	0	0	290173232	289998595	0	0
tb.dut.KmacDataODataKnown_A	0	0	290173232	246941686	0	0
tb.dut.KmacDataODataKnown_AKnownEnable	0	0	290173232	289998595	0	0
tb.dut.KmacDataOValidKnown_A	0	0	290173232	289998595	0	0
tb.dut.PwrmgrDataOKnown_A	0	0	290173232	289998595	0	0
tb.dut.RegsTlOAReadyKnown_A	0	0	290173232	289998595	0	0
tb.dut.RegsTlODDataKnown_A	0	0	290173232	4771238	0	0
tb.dut.RegsTlODDataKnown_AKnownEnable	0	0	290173232	289998595	0	0
tb.dut.RegsTlODValidKnown_A	0	0	290173232	289998595	0	0
tb.dut.RomTlOAReadyKnown_A	0	0	290173232	289998595	0	0
tb.dut.RomTlODDataKnown_A	0	0	290173232	5857825	0	0
tb.dut.RomTlODDataKnown_AKnownEnable	0	0	290173232	289998595	0	0
tb.dut.RomTlODValidKnown_A	0	0	290173232	289998595	0	0
tb.dut.StabilityChkKmac_A	0	0	290173232	246939320	0	0
tb.dut.StabilityChkkeymgr_A	0	0	290173232	42928481	0	0
tb.dut.TlAccessChk_A	0	0	290173232	247068972	0	0
tb.dut.gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A	0	0	290173232	80	0	0
tb.dut.gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A	0	0	290173232	477	0	0
tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.LastImpliesValid_A	0	0	290173232	15177	0	0
tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.RelAddrWide_A	0	0	290173232	10404	0	0
tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_compare.NumWordsPositive_A	0	0	314	314	0	0
tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_compare.u_done_sender.OutputsKnown_A	0	0	290173232	289998595	0	0
tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_compare.u_state_regs.AssertConnected_A	0	0	314	314	0	0
tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_compare.u_state_regs_A	0	0	290173232	289998595	0	0
tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_counter.NonTopCountValid_A	0	0	314	314	0	0
tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_counter.TopCountValid_A	0	0	314	314	0	0
tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_state_regs.AssertConnected_A	0	0	314	314	0	0
tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_state_regs_A	0	0	290173232	289998595	0	0
tb.dut.gen_rom_scramble_enabled.u_rom.DepthPow2Check_A	0	0	314	314	0	0
tb.dut.gen_rom_scramble_enabled.u_rom.MaxWidthCheck_A	0	0	314	314	0	0
tb.dut.gen_rom_scramble_enabled.u_rom.u_rom.noXOnCsI	0	0	290173232	290173232	0	0
tb.dut.gen_rom_scramble_enabled.u_rom.u_rom.u_prim_rom.gen_generic.u_impl_generic.noXOnCsI	0	0	290173232	290173232	0	0
tb.dut.regs_tlul_assert_device.aKnown_A	0	0	327746770	3945661	0	0
tb.dut.regs_tlul_assert_device.aKnown_AKnownEnable	0	0	327746770	327505194	0	0
tb.dut.regs_tlul_assert_device.aReadyKnown_A	0	0	327746770	327505194	0	0
tb.dut.regs_tlul_assert_device.dKnown_A	0	0	327746770	4852083	0	0
tb.dut.regs_tlul_assert_device.dKnown_AKnownEnable	0	0	327746770	327505194	0	0
tb.dut.regs_tlul_assert_device.dReadyKnown_A	0	0	327746770	327505194	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[19].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[201].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[202].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[203].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[204].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[205].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[206].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[207].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[208].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[209].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[20].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[210].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[211].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[212].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[213].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
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tb.dut.regs_tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.regs_tlul_assert_device.gen_device.aDataKnown_M	0	0	327747055	3241615	0	0
tb.dut.regs_tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	327746770	674547	0	0
tb.dut.regs_tlul_assert_device.gen_device.contigMask_M	0	0	327747055	13662	0	0
tb.dut.regs_tlul_assert_device.gen_device.dDataKnown_A	0	0	327747055	20425	0	0
tb.dut.regs_tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	327746770	755875	0	0
tb.dut.regs_tlul_assert_device.gen_device.legalAParam_M	0	0	327747055	3945661	0	0
tb.dut.regs_tlul_assert_device.gen_device.legalDParam_A	0	0	327747055	4852083	0	0
tb.dut.regs_tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	327747055	3945661	0	0
tb.dut.regs_tlul_assert_device.gen_device.respMustHaveReq_A	0	0	327747055	4852083	0	0
tb.dut.regs_tlul_assert_device.gen_device.respOpcode_A	0	0	327747055	4852083	0	0
tb.dut.regs_tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	327747055	4852083	0	0
tb.dut.regs_tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	327746770	408786	0	0
tb.dut.regs_tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	327746770	285020	0	0
tb.dut.regs_tlul_assert_device.p_dbw.TlDbw_A	0	0	459	459	0	0
tb.dut.rom_ctrl_regs_csr_assert.TlulOOBAddrErr_A	0	0	327746770	1454908	0	0
tb.dut.rom_tlul_assert_device.aKnown_A	0	0	327746770	43145960	0	0
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tb.dut.rom_tlul_assert_device.aReadyKnown_A	0	0	327746770	327505194	0	0
tb.dut.rom_tlul_assert_device.dKnown_A	0	0	327746770	5923249	0	0
tb.dut.rom_tlul_assert_device.dKnown_AKnownEnable	0	0	327746770	327505194	0	0
tb.dut.rom_tlul_assert_device.dReadyKnown_A	0	0	327746770	327505194	0	0
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tb.dut.rom_tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
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tb.dut.rom_tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
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tb.dut.rom_tlul_assert_device.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	459	459	0	0
tb.dut.rom_tlul_assert_device.gen_device.aDataKnown_M	0	0	327747055	2911968	0	0
tb.dut.rom_tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	327746770	873592	0	0
tb.dut.rom_tlul_assert_device.gen_device.contigMask_M	0	0	327747055	38810378	0	0
tb.dut.rom_tlul_assert_device.gen_device.dDataKnown_A	0	0	327747055	41941	0	0
tb.dut.rom_tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	327746770	1121950	0	0
tb.dut.rom_tlul_assert_device.gen_device.legalAParam_M	0	0	327747055	43145960	0	0
tb.dut.rom_tlul_assert_device.gen_device.legalDParam_A	0	0	327747055	5923249	0	0
tb.dut.rom_tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	327747055	43145960	0	0
tb.dut.rom_tlul_assert_device.gen_device.respMustHaveReq_A	0	0	327747055	5923249	0	0
tb.dut.rom_tlul_assert_device.gen_device.respOpcode_A	0	0	327747055	5923249	0	0
tb.dut.rom_tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	327747055	5923249	0	0
tb.dut.rom_tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	327746770	482635	0	0
tb.dut.rom_tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	327746770	263156	0	0
tb.dut.rom_tlul_assert_device.p_dbw.TlDbw_A	0	0	459	459	0	0
tb.dut.u_reg_regs.en2addrHit	0	0	327746770	95979	0	0
tb.dut.u_reg_regs.reAfterRv	0	0	327746770	95979	0	0
tb.dut.u_reg_regs.rePulse	0	0	327746770	27357	0	0
tb.dut.u_reg_regs.u_chk.PayLoadWidthCheck	0	0	459	459	0	0
tb.dut.u_reg_regs.u_reg_if.AllowedLatency_A	0	0	459	459	0	0
tb.dut.u_reg_regs.u_reg_if.MatchedWidthAssert	0	0	459	459	0	0
tb.dut.u_reg_regs.u_reg_if.u_err.dataWidthOnly32_A	0	0	459	459	0	0
tb.dut.u_reg_regs.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	459	459	0	0
tb.dut.u_reg_regs.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	459	459	0	0
tb.dut.u_reg_regs.u_rsp_intg_gen.DataWidthCheck_A	0	0	459	459	0	0
tb.dut.u_reg_regs.u_rsp_intg_gen.PayLoadWidthCheck	0	0	459	459	0	0
tb.dut.u_reg_regs.wePulse	0	0	327746770	68622	0	0
tb.dut.u_tl_adapter_rom.AddrOutKnown_A	0	0	290173232	289998595	0	0
tb.dut.u_tl_adapter_rom.DataIntgOptions_A	0	0	314	314	0	0
tb.dut.u_tl_adapter_rom.ReqOutKnown_A	0	0	290173232	289998595	0	0
tb.dut.u_tl_adapter_rom.SramDwHasByteGranularity_A	0	0	314	314	0	0
tb.dut.u_tl_adapter_rom.SramDwIsMultipleOfTlulWidth_A	0	0	314	314	0	0
tb.dut.u_tl_adapter_rom.TlOutKnownIfFifoKnown_A	0	0	290173232	289998595	0	0
tb.dut.u_tl_adapter_rom.TlOutValidKnown_A	0	0	290173232	289998595	0	0
tb.dut.u_tl_adapter_rom.WdataOutKnown_A	0	0	290173232	289998595	0	0
tb.dut.u_tl_adapter_rom.WeOutKnown_A	0	0	290173232	289998595	0	0
tb.dut.u_tl_adapter_rom.WmaskOutKnown_A	0	0	290173232	289998595	0	0
tb.dut.u_tl_adapter_rom.adapterNoReadOrWrite	0	0	314	314	0	0
tb.dut.u_tl_adapter_rom.gen_cmd_intg_check.u_cmd_intg_chk.PayLoadWidthCheck	0	0	314	314	0	0
tb.dut.u_tl_adapter_rom.rvalidHighReqFifoEmpty	0	0	290173232	32425	0	0
tb.dut.u_tl_adapter_rom.rvalidHighWhenRspFifoFull	0	0	290173232	32425	0	0
tb.dut.u_tl_adapter_rom.u_err.dataWidthOnly32_A	0	0	314	314	0	0
tb.dut.u_tl_adapter_rom.u_reqfifo.DataKnown_A	0	0	290173232	5857825	0	0
tb.dut.u_tl_adapter_rom.u_reqfifo.DepthKnown_A	0	0	290173232	289998595	0	0
tb.dut.u_tl_adapter_rom.u_reqfifo.RvalidKnown_A	0	0	290173232	289998595	0	0
tb.dut.u_tl_adapter_rom.u_reqfifo.WreadyKnown_A	0	0	290173232	289998595	0	0
tb.dut.u_tl_adapter_rom.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	290173232	5857825	0	0
tb.dut.u_tl_adapter_rom.u_rsp_gen.DataWidthCheck_A	0	0	314	314	0	0
tb.dut.u_tl_adapter_rom.u_rsp_gen.PayLoadWidthCheck	0	0	314	314	0	0
tb.dut.u_tl_adapter_rom.u_rspfifo.DataKnown_A	0	0	290173232	58031	0	0
tb.dut.u_tl_adapter_rom.u_rspfifo.DepthKnown_A	0	0	290173232	289998595	0	0
tb.dut.u_tl_adapter_rom.u_rspfifo.RvalidKnown_A	0	0	290173232	289998595	0	0
tb.dut.u_tl_adapter_rom.u_rspfifo.WreadyKnown_A	0	0	290173232	289998595	0	0
tb.dut.u_tl_adapter_rom.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	290173232	58031	0	0
tb.dut.u_tl_adapter_rom.u_sram_byte.SramReadbackAndIntg	0	0	314	314	0	0
tb.dut.u_tl_adapter_rom.u_sramreqfifo.DataKnown_A	0	0	290173232	32425	0	0
tb.dut.u_tl_adapter_rom.u_sramreqfifo.DepthKnown_A	0	0	290173232	289998595	0	0
tb.dut.u_tl_adapter_rom.u_sramreqfifo.RvalidKnown_A	0	0	290173232	289998595	0	0
tb.dut.u_tl_adapter_rom.u_sramreqfifo.WreadyKnown_A	0	0	290173232	289998595	0	0
tb.dut.u_tl_adapter_rom.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	290173232	32425	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.KeymgrValidChk_A	0	0	290173232	0	0	314
tb.dut.PwrmgrDataChk_A	0	0	290173232	0	0	314
tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.SecCmCFILinear_A	0	0	290173232	0	0	1254

---

Detail Report for Cover Sequences

Cover Sequences Uncovered:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.rom_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	327747055	0	0	0
tb.dut.rom_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	327747055	0	0	0
tb.dut.rom_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	327747055	0	0	0
tb.dut.rom_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	327747055	0	0	0
tb.dut.rom_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	327747055	0	0	0
tb.dut.rom_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	327747055	0	0	0
tb.dut.rom_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	327747055	0	0	0

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.regs_tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	327747055	205	205	0
tb.dut.regs_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	327747055	48	48	2
tb.dut.regs_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	327747055	50	50	2
tb.dut.regs_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	327747055	11	11	2
tb.dut.regs_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	327747055	27	27	2
tb.dut.regs_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	327747055	9	9	2
tb.dut.regs_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	327747055	25	25	2
tb.dut.regs_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	327747055	677	677	0
tb.dut.regs_tlul_assert_device.gen_device_cov.b2bReq_C	0	0	327747055	1390	1390	0
tb.dut.regs_tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	327747055	4638	4638	190
tb.dut.rom_tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	327747055	1500559	1500559	0
tb.dut.rom_tlul_assert_device.gen_device_cov.b2bReq_C	0	0	327747055	13509	13509	0
tb.dut.rom_tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	327747055	357	357	137

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.regs_tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	327747055	205	205	0
tb.dut.regs_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	327747055	48	48	2
tb.dut.regs_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	327747055	50	50	2
tb.dut.regs_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	327747055	11	11	2
tb.dut.regs_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	327747055	27	27	2
tb.dut.regs_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	327747055	9	9	2
tb.dut.regs_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	327747055	25	25	2
tb.dut.regs_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	327747055	677	677	0
tb.dut.regs_tlul_assert_device.gen_device_cov.b2bReq_C	0	0	327747055	1390	1390	0
tb.dut.regs_tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	327747055	4638	4638	190
tb.dut.rom_tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	327747055	1500559	1500559	0
tb.dut.rom_tlul_assert_device.gen_device_cov.b2bReq_C	0	0	327747055	13509	13509	0
tb.dut.rom_tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	327747055	357	357	137