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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.19 96.89 91.85 97.68 100.00 98.28 97.30 98.37


Total test records in report: 459
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T299 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1832115013 Jul 07 04:51:07 PM PDT 24 Jul 07 04:51:37 PM PDT 24 5482435476 ps
T300 /workspace/coverage/default/19.rom_ctrl_alert_test.3368259943 Jul 07 04:50:45 PM PDT 24 Jul 07 04:51:18 PM PDT 24 7664667421 ps
T301 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.10676401 Jul 07 04:50:58 PM PDT 24 Jul 07 05:01:54 PM PDT 24 216447023495 ps
T302 /workspace/coverage/default/15.rom_ctrl_stress_all.622309316 Jul 07 04:50:37 PM PDT 24 Jul 07 04:53:47 PM PDT 24 78236988274 ps
T303 /workspace/coverage/default/24.rom_ctrl_alert_test.434480889 Jul 07 04:51:00 PM PDT 24 Jul 07 04:51:15 PM PDT 24 3558676796 ps
T304 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2706879849 Jul 07 04:50:13 PM PDT 24 Jul 07 04:50:33 PM PDT 24 345890776 ps
T305 /workspace/coverage/default/8.rom_ctrl_alert_test.4069468466 Jul 07 04:50:19 PM PDT 24 Jul 07 04:50:28 PM PDT 24 2062037291 ps
T306 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.980649186 Jul 07 04:50:18 PM PDT 24 Jul 07 04:51:09 PM PDT 24 20559941684 ps
T307 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1811191989 Jul 07 04:50:18 PM PDT 24 Jul 07 04:50:37 PM PDT 24 5169860520 ps
T308 /workspace/coverage/default/23.rom_ctrl_stress_all.3529506656 Jul 07 04:50:50 PM PDT 24 Jul 07 04:52:27 PM PDT 24 27612683552 ps
T309 /workspace/coverage/default/39.rom_ctrl_stress_all.1501647560 Jul 07 04:51:22 PM PDT 24 Jul 07 04:52:42 PM PDT 24 8334274293 ps
T310 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3203919082 Jul 07 04:51:51 PM PDT 24 Jul 07 04:52:22 PM PDT 24 21857063497 ps
T311 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3817360533 Jul 07 04:51:29 PM PDT 24 Jul 07 04:51:49 PM PDT 24 1657361315 ps
T312 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.576930212 Jul 07 04:50:18 PM PDT 24 Jul 07 04:50:38 PM PDT 24 1486177872 ps
T313 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2386403571 Jul 07 04:50:23 PM PDT 24 Jul 07 04:50:42 PM PDT 24 1739145232 ps
T314 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2382376667 Jul 07 04:51:31 PM PDT 24 Jul 07 04:54:29 PM PDT 24 5010693634 ps
T315 /workspace/coverage/default/13.rom_ctrl_alert_test.2600530380 Jul 07 04:50:33 PM PDT 24 Jul 07 04:50:42 PM PDT 24 688751678 ps
T47 /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.4035019919 Jul 07 04:50:08 PM PDT 24 Jul 07 04:59:30 PM PDT 24 14418792687 ps
T48 /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.2955418370 Jul 07 04:51:18 PM PDT 24 Jul 07 05:06:35 PM PDT 24 91727222516 ps
T316 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2753263998 Jul 07 04:50:21 PM PDT 24 Jul 07 04:50:50 PM PDT 24 16536413203 ps
T317 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.4108574 Jul 07 04:51:08 PM PDT 24 Jul 07 04:52:16 PM PDT 24 8438185769 ps
T318 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1020514795 Jul 07 04:51:28 PM PDT 24 Jul 07 05:02:46 PM PDT 24 68776952601 ps
T319 /workspace/coverage/default/14.rom_ctrl_smoke.4161509038 Jul 07 04:50:33 PM PDT 24 Jul 07 04:50:54 PM PDT 24 714262266 ps
T320 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2564540561 Jul 07 04:50:11 PM PDT 24 Jul 07 04:50:35 PM PDT 24 11870834064 ps
T321 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1125272411 Jul 07 04:51:05 PM PDT 24 Jul 07 04:51:21 PM PDT 24 1520039998 ps
T322 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2661304892 Jul 07 04:51:03 PM PDT 24 Jul 07 04:51:14 PM PDT 24 694220825 ps
T323 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.4176446955 Jul 07 04:50:15 PM PDT 24 Jul 07 04:56:46 PM PDT 24 128806595621 ps
T324 /workspace/coverage/default/2.rom_ctrl_stress_all.2270033782 Jul 07 04:50:07 PM PDT 24 Jul 07 04:50:43 PM PDT 24 4945888421 ps
T325 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3476236556 Jul 07 04:50:08 PM PDT 24 Jul 07 04:53:26 PM PDT 24 5400875995 ps
T326 /workspace/coverage/default/15.rom_ctrl_alert_test.1838753329 Jul 07 04:50:38 PM PDT 24 Jul 07 04:50:54 PM PDT 24 4255562735 ps
T327 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3790169111 Jul 07 04:50:13 PM PDT 24 Jul 07 04:53:20 PM PDT 24 2922588753 ps
T328 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1919869788 Jul 07 04:50:12 PM PDT 24 Jul 07 05:02:19 PM PDT 24 292330777003 ps
T329 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2576962791 Jul 07 04:50:59 PM PDT 24 Jul 07 04:51:19 PM PDT 24 1501989700 ps
T330 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2457954760 Jul 07 04:51:35 PM PDT 24 Jul 07 04:59:13 PM PDT 24 50257703645 ps
T331 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1769575422 Jul 07 04:50:11 PM PDT 24 Jul 07 04:50:30 PM PDT 24 1270646893 ps
T332 /workspace/coverage/default/11.rom_ctrl_smoke.994586764 Jul 07 04:50:20 PM PDT 24 Jul 07 04:51:30 PM PDT 24 7344115371 ps
T333 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.4005430478 Jul 07 04:50:11 PM PDT 24 Jul 07 04:50:35 PM PDT 24 1713053872 ps
T49 /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.695611771 Jul 07 04:50:23 PM PDT 24 Jul 07 05:37:17 PM PDT 24 147586380804 ps
T334 /workspace/coverage/default/24.rom_ctrl_stress_all.2783731032 Jul 07 04:50:59 PM PDT 24 Jul 07 04:52:54 PM PDT 24 13889714941 ps
T335 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1246299288 Jul 07 04:50:10 PM PDT 24 Jul 07 04:50:20 PM PDT 24 698530352 ps
T336 /workspace/coverage/default/35.rom_ctrl_smoke.2413942126 Jul 07 04:51:12 PM PDT 24 Jul 07 04:51:48 PM PDT 24 2342802487 ps
T337 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2293282623 Jul 07 04:50:32 PM PDT 24 Jul 07 04:50:52 PM PDT 24 502996055 ps
T338 /workspace/coverage/default/42.rom_ctrl_alert_test.4094930948 Jul 07 04:51:33 PM PDT 24 Jul 07 04:51:42 PM PDT 24 660933380 ps
T339 /workspace/coverage/default/3.rom_ctrl_smoke.3471804927 Jul 07 04:50:09 PM PDT 24 Jul 07 04:50:28 PM PDT 24 1233608541 ps
T340 /workspace/coverage/default/5.rom_ctrl_alert_test.2619562211 Jul 07 04:50:13 PM PDT 24 Jul 07 04:50:37 PM PDT 24 9911984655 ps
T341 /workspace/coverage/default/33.rom_ctrl_smoke.1382349960 Jul 07 04:51:08 PM PDT 24 Jul 07 04:51:36 PM PDT 24 5811062099 ps
T342 /workspace/coverage/default/33.rom_ctrl_alert_test.2800100471 Jul 07 04:51:08 PM PDT 24 Jul 07 04:51:27 PM PDT 24 3163398812 ps
T343 /workspace/coverage/default/3.rom_ctrl_alert_test.2594747021 Jul 07 04:50:14 PM PDT 24 Jul 07 04:50:37 PM PDT 24 9178263164 ps
T344 /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1949842675 Jul 07 04:51:51 PM PDT 24 Jul 07 04:52:11 PM PDT 24 332793230 ps
T345 /workspace/coverage/default/33.rom_ctrl_stress_all.876508127 Jul 07 04:51:08 PM PDT 24 Jul 07 04:53:24 PM PDT 24 8998879602 ps
T346 /workspace/coverage/default/22.rom_ctrl_stress_all.2667909636 Jul 07 04:50:51 PM PDT 24 Jul 07 04:51:28 PM PDT 24 3286734861 ps
T347 /workspace/coverage/default/21.rom_ctrl_alert_test.215640691 Jul 07 04:50:51 PM PDT 24 Jul 07 04:51:21 PM PDT 24 7009695874 ps
T348 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1345709640 Jul 07 04:51:44 PM PDT 24 Jul 07 04:51:58 PM PDT 24 4556232679 ps
T349 /workspace/coverage/default/1.rom_ctrl_stress_all.973256607 Jul 07 04:50:10 PM PDT 24 Jul 07 04:51:10 PM PDT 24 60802271559 ps
T350 /workspace/coverage/default/46.rom_ctrl_smoke.3330970921 Jul 07 04:51:44 PM PDT 24 Jul 07 04:52:14 PM PDT 24 1491922673 ps
T351 /workspace/coverage/default/37.rom_ctrl_smoke.4178650519 Jul 07 04:51:11 PM PDT 24 Jul 07 04:51:32 PM PDT 24 3359007915 ps
T352 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.173990441 Jul 07 04:50:21 PM PDT 24 Jul 07 04:50:56 PM PDT 24 19138044302 ps
T353 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3897583579 Jul 07 04:50:08 PM PDT 24 Jul 07 04:53:02 PM PDT 24 52867493095 ps
T354 /workspace/coverage/default/12.rom_ctrl_smoke.2314821656 Jul 07 04:50:27 PM PDT 24 Jul 07 04:51:25 PM PDT 24 79739590523 ps
T355 /workspace/coverage/default/42.rom_ctrl_smoke.2120583101 Jul 07 04:51:30 PM PDT 24 Jul 07 04:51:51 PM PDT 24 355118380 ps
T50 /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.20448034 Jul 07 04:50:23 PM PDT 24 Jul 07 05:09:49 PM PDT 24 60698947770 ps
T356 /workspace/coverage/default/46.rom_ctrl_alert_test.1031345001 Jul 07 04:51:45 PM PDT 24 Jul 07 04:52:19 PM PDT 24 16336834510 ps
T357 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.44450019 Jul 07 04:50:57 PM PDT 24 Jul 07 04:51:26 PM PDT 24 3298706086 ps
T358 /workspace/coverage/default/22.rom_ctrl_smoke.358851042 Jul 07 04:50:49 PM PDT 24 Jul 07 04:51:36 PM PDT 24 4529804474 ps
T61 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3569859531 Jul 07 04:50:01 PM PDT 24 Jul 07 04:50:23 PM PDT 24 4501939334 ps
T57 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1788611068 Jul 07 04:50:01 PM PDT 24 Jul 07 04:52:52 PM PDT 24 4295543128 ps
T62 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.177059166 Jul 07 04:49:51 PM PDT 24 Jul 07 04:50:01 PM PDT 24 970978771 ps
T67 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.318639821 Jul 07 04:50:00 PM PDT 24 Jul 07 04:50:38 PM PDT 24 4556628050 ps
T58 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.4294156684 Jul 07 04:49:50 PM PDT 24 Jul 07 04:52:46 PM PDT 24 4056876858 ps
T59 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2505412544 Jul 07 04:50:01 PM PDT 24 Jul 07 04:51:22 PM PDT 24 274679344 ps
T359 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1292140828 Jul 07 04:49:47 PM PDT 24 Jul 07 04:50:09 PM PDT 24 2064829278 ps
T68 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3901484418 Jul 07 04:50:05 PM PDT 24 Jul 07 04:50:36 PM PDT 24 8029612326 ps
T69 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3860420575 Jul 07 04:50:04 PM PDT 24 Jul 07 04:50:49 PM PDT 24 4229546379 ps
T360 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.226969809 Jul 07 04:49:51 PM PDT 24 Jul 07 04:50:01 PM PDT 24 172572117 ps
T95 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3739408451 Jul 07 04:50:00 PM PDT 24 Jul 07 04:50:30 PM PDT 24 3444188755 ps
T102 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3496878490 Jul 07 04:50:03 PM PDT 24 Jul 07 04:52:56 PM PDT 24 7287587047 ps
T70 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1014500964 Jul 07 04:49:48 PM PDT 24 Jul 07 04:50:11 PM PDT 24 6912280503 ps
T361 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2801353033 Jul 07 04:49:48 PM PDT 24 Jul 07 04:51:12 PM PDT 24 283255223 ps
T71 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2323126360 Jul 07 04:50:02 PM PDT 24 Jul 07 04:50:30 PM PDT 24 6535567972 ps
T72 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.955651321 Jul 07 04:50:04 PM PDT 24 Jul 07 04:50:26 PM PDT 24 2084505159 ps
T96 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3356192676 Jul 07 04:49:56 PM PDT 24 Jul 07 04:50:09 PM PDT 24 667261933 ps
T101 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.4071302983 Jul 07 04:50:00 PM PDT 24 Jul 07 04:50:56 PM PDT 24 4127650108 ps
T105 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1569122747 Jul 07 04:49:45 PM PDT 24 Jul 07 04:51:26 PM PDT 24 7649328487 ps
T89 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.4070740616 Jul 07 04:50:04 PM PDT 24 Jul 07 04:50:19 PM PDT 24 852538448 ps
T362 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3457475805 Jul 07 04:50:01 PM PDT 24 Jul 07 04:50:19 PM PDT 24 1451483359 ps
T73 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1730623704 Jul 07 04:49:48 PM PDT 24 Jul 07 04:50:11 PM PDT 24 5740713134 ps
T363 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3235132472 Jul 07 04:49:45 PM PDT 24 Jul 07 04:50:11 PM PDT 24 19255304825 ps
T74 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.710992131 Jul 07 04:49:48 PM PDT 24 Jul 07 04:52:09 PM PDT 24 27186233412 ps
T364 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1358363227 Jul 07 04:49:44 PM PDT 24 Jul 07 04:50:42 PM PDT 24 1037923154 ps
T107 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3665991745 Jul 07 04:50:01 PM PDT 24 Jul 07 04:52:51 PM PDT 24 9716987715 ps
T108 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3272742620 Jul 07 04:49:49 PM PDT 24 Jul 07 04:52:31 PM PDT 24 6993291377 ps
T79 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.754290023 Jul 07 04:50:00 PM PDT 24 Jul 07 04:50:13 PM PDT 24 1285227945 ps
T365 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2489724 Jul 07 04:50:03 PM PDT 24 Jul 07 04:50:18 PM PDT 24 4191755019 ps
T366 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2177051572 Jul 07 04:49:51 PM PDT 24 Jul 07 04:50:20 PM PDT 24 3205889939 ps
T106 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3529346588 Jul 07 04:50:04 PM PDT 24 Jul 07 04:51:25 PM PDT 24 471635187 ps
T367 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3422461330 Jul 07 04:49:48 PM PDT 24 Jul 07 04:50:13 PM PDT 24 7605045641 ps
T368 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2164772094 Jul 07 04:49:51 PM PDT 24 Jul 07 04:51:15 PM PDT 24 8673701425 ps
T90 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.528855789 Jul 07 04:49:46 PM PDT 24 Jul 07 04:50:17 PM PDT 24 40033861465 ps
T369 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2317011860 Jul 07 04:49:59 PM PDT 24 Jul 07 04:50:14 PM PDT 24 2992242492 ps
T109 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3317144659 Jul 07 04:49:42 PM PDT 24 Jul 07 04:51:19 PM PDT 24 18568301074 ps
T103 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2106742278 Jul 07 04:50:00 PM PDT 24 Jul 07 04:52:36 PM PDT 24 2485410207 ps
T91 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1022969488 Jul 07 04:50:04 PM PDT 24 Jul 07 04:50:28 PM PDT 24 4791186187 ps
T92 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.909636226 Jul 07 04:50:04 PM PDT 24 Jul 07 04:50:34 PM PDT 24 3781057295 ps
T370 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1904332463 Jul 07 04:49:55 PM PDT 24 Jul 07 04:51:19 PM PDT 24 663118570 ps
T371 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2193909900 Jul 07 04:50:03 PM PDT 24 Jul 07 04:50:22 PM PDT 24 2856288336 ps
T80 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1424461971 Jul 07 04:49:52 PM PDT 24 Jul 07 04:51:39 PM PDT 24 25350037071 ps
T372 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2357828184 Jul 07 04:49:50 PM PDT 24 Jul 07 04:50:18 PM PDT 24 3473394942 ps
T373 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3912661378 Jul 07 04:49:58 PM PDT 24 Jul 07 04:50:27 PM PDT 24 3622817970 ps
T374 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.4183210493 Jul 07 04:49:47 PM PDT 24 Jul 07 04:50:13 PM PDT 24 2994489528 ps
T81 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3412676284 Jul 07 04:50:01 PM PDT 24 Jul 07 04:51:32 PM PDT 24 5688919151 ps
T375 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.4178253005 Jul 07 04:49:57 PM PDT 24 Jul 07 04:50:17 PM PDT 24 4777332299 ps
T112 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2260176712 Jul 07 04:50:04 PM PDT 24 Jul 07 04:53:00 PM PDT 24 8384919382 ps
T376 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.292264216 Jul 07 04:49:56 PM PDT 24 Jul 07 04:50:29 PM PDT 24 13453940617 ps
T82 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2256862966 Jul 07 04:49:50 PM PDT 24 Jul 07 04:50:47 PM PDT 24 11034963005 ps
T104 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2752935447 Jul 07 04:49:47 PM PDT 24 Jul 07 04:51:22 PM PDT 24 2658716843 ps
T93 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3618924687 Jul 07 04:50:03 PM PDT 24 Jul 07 04:50:28 PM PDT 24 5590169810 ps
T94 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.235631825 Jul 07 04:49:53 PM PDT 24 Jul 07 04:50:06 PM PDT 24 175680707 ps
T377 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3911698164 Jul 07 04:50:02 PM PDT 24 Jul 07 04:50:42 PM PDT 24 4182536775 ps
T378 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3439614905 Jul 07 04:49:48 PM PDT 24 Jul 07 04:50:18 PM PDT 24 3625337982 ps
T379 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2349791197 Jul 07 04:50:03 PM PDT 24 Jul 07 04:50:18 PM PDT 24 1032819341 ps
T380 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3889024516 Jul 07 04:50:03 PM PDT 24 Jul 07 04:50:20 PM PDT 24 15375237555 ps
T87 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4018851924 Jul 07 04:49:43 PM PDT 24 Jul 07 04:49:59 PM PDT 24 1015627670 ps
T381 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.547413399 Jul 07 04:50:04 PM PDT 24 Jul 07 04:50:27 PM PDT 24 9251403340 ps
T382 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3264604712 Jul 07 04:50:00 PM PDT 24 Jul 07 04:50:29 PM PDT 24 7481099421 ps
T383 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2392563371 Jul 07 04:49:46 PM PDT 24 Jul 07 04:50:08 PM PDT 24 7814959670 ps
T384 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4071083593 Jul 07 04:49:50 PM PDT 24 Jul 07 04:50:09 PM PDT 24 1910215162 ps
T111 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.82845141 Jul 07 04:49:57 PM PDT 24 Jul 07 04:52:41 PM PDT 24 2253017219 ps
T385 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3935952747 Jul 07 04:49:53 PM PDT 24 Jul 07 04:50:03 PM PDT 24 586850049 ps
T386 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2400823933 Jul 07 04:49:50 PM PDT 24 Jul 07 04:50:27 PM PDT 24 6338070139 ps
T83 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.569990906 Jul 07 04:49:48 PM PDT 24 Jul 07 04:50:21 PM PDT 24 16371837987 ps
T387 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.241948768 Jul 07 04:50:03 PM PDT 24 Jul 07 04:50:12 PM PDT 24 661616040 ps
T388 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3117165925 Jul 07 04:49:55 PM PDT 24 Jul 07 04:50:22 PM PDT 24 21576106913 ps
T389 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1557107491 Jul 07 04:49:56 PM PDT 24 Jul 07 04:50:25 PM PDT 24 3419374784 ps
T390 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3582491648 Jul 07 04:50:03 PM PDT 24 Jul 07 04:51:31 PM PDT 24 34224520299 ps
T391 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4249707446 Jul 07 04:49:49 PM PDT 24 Jul 07 04:49:59 PM PDT 24 366301820 ps
T84 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.64032982 Jul 07 04:49:49 PM PDT 24 Jul 07 04:50:22 PM PDT 24 3950919874 ps
T392 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3112416814 Jul 07 04:49:42 PM PDT 24 Jul 07 04:50:02 PM PDT 24 1367684754 ps
T393 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1347237523 Jul 07 04:50:04 PM PDT 24 Jul 07 04:52:43 PM PDT 24 5301871215 ps
T394 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.514573537 Jul 07 04:49:51 PM PDT 24 Jul 07 04:50:30 PM PDT 24 689782846 ps
T395 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3939689075 Jul 07 04:49:50 PM PDT 24 Jul 07 04:50:01 PM PDT 24 293267447 ps
T396 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.61324839 Jul 07 04:49:42 PM PDT 24 Jul 07 04:49:59 PM PDT 24 1227886702 ps
T397 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1914928955 Jul 07 04:50:05 PM PDT 24 Jul 07 04:50:25 PM PDT 24 937546335 ps
T398 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3374976190 Jul 07 04:50:05 PM PDT 24 Jul 07 04:50:32 PM PDT 24 4030854151 ps
T399 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3799277282 Jul 07 04:49:42 PM PDT 24 Jul 07 04:50:00 PM PDT 24 6195181672 ps
T400 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.394609878 Jul 07 04:49:49 PM PDT 24 Jul 07 04:50:18 PM PDT 24 11282846322 ps
T85 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1775172331 Jul 07 04:50:03 PM PDT 24 Jul 07 04:52:04 PM PDT 24 14136106736 ps
T401 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1417693139 Jul 07 04:50:02 PM PDT 24 Jul 07 04:50:27 PM PDT 24 25511800409 ps
T402 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.217748302 Jul 07 04:50:04 PM PDT 24 Jul 07 04:50:37 PM PDT 24 17944186304 ps
T403 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2300254411 Jul 07 04:49:44 PM PDT 24 Jul 07 04:50:15 PM PDT 24 12370626792 ps
T404 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2768127104 Jul 07 04:50:00 PM PDT 24 Jul 07 04:50:32 PM PDT 24 21102378646 ps
T405 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.17510877 Jul 07 04:49:50 PM PDT 24 Jul 07 04:50:08 PM PDT 24 1357929979 ps
T406 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3534368025 Jul 07 04:49:56 PM PDT 24 Jul 07 04:50:08 PM PDT 24 184041547 ps
T407 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3167244425 Jul 07 04:49:54 PM PDT 24 Jul 07 04:50:18 PM PDT 24 2557057147 ps
T408 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.464719259 Jul 07 04:49:45 PM PDT 24 Jul 07 04:49:59 PM PDT 24 4138418583 ps
T409 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1710021610 Jul 07 04:49:48 PM PDT 24 Jul 07 04:50:02 PM PDT 24 2632561023 ps
T410 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3237021958 Jul 07 04:49:54 PM PDT 24 Jul 07 04:50:08 PM PDT 24 167754901 ps
T411 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.852547773 Jul 07 04:49:45 PM PDT 24 Jul 07 04:50:06 PM PDT 24 2045134207 ps
T412 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2202371487 Jul 07 04:49:51 PM PDT 24 Jul 07 04:50:18 PM PDT 24 2493711898 ps
T88 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4047948961 Jul 07 04:49:51 PM PDT 24 Jul 07 04:50:49 PM PDT 24 1068861630 ps
T413 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1245604580 Jul 07 04:49:50 PM PDT 24 Jul 07 04:50:23 PM PDT 24 15747710666 ps
T414 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3292323379 Jul 07 04:49:43 PM PDT 24 Jul 07 04:49:55 PM PDT 24 1024838847 ps
T415 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2671265604 Jul 07 04:49:49 PM PDT 24 Jul 07 04:50:06 PM PDT 24 1183789171 ps
T416 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1726438730 Jul 07 04:49:44 PM PDT 24 Jul 07 04:49:53 PM PDT 24 360399718 ps
T417 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.433888779 Jul 07 04:50:02 PM PDT 24 Jul 07 04:50:21 PM PDT 24 1743277767 ps
T418 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2262009969 Jul 07 04:49:56 PM PDT 24 Jul 07 04:50:26 PM PDT 24 9359894441 ps
T419 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3230011720 Jul 07 04:50:01 PM PDT 24 Jul 07 04:50:17 PM PDT 24 4079941772 ps
T420 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2865295105 Jul 07 04:49:50 PM PDT 24 Jul 07 04:50:05 PM PDT 24 916303575 ps
T421 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2187933068 Jul 07 04:49:55 PM PDT 24 Jul 07 04:52:45 PM PDT 24 2679518998 ps
T422 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3716821067 Jul 07 04:49:46 PM PDT 24 Jul 07 04:50:17 PM PDT 24 38327628780 ps
T423 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1480525185 Jul 07 04:49:56 PM PDT 24 Jul 07 04:50:08 PM PDT 24 1648868246 ps
T424 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.882229072 Jul 07 04:50:02 PM PDT 24 Jul 07 04:50:31 PM PDT 24 6836963204 ps
T425 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2680459477 Jul 07 04:50:03 PM PDT 24 Jul 07 04:51:55 PM PDT 24 8748363146 ps
T426 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1651713172 Jul 07 04:49:44 PM PDT 24 Jul 07 04:50:08 PM PDT 24 43075404925 ps
T427 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3763840226 Jul 07 04:49:41 PM PDT 24 Jul 07 04:49:58 PM PDT 24 3091506589 ps
T428 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2024093458 Jul 07 04:50:06 PM PDT 24 Jul 07 04:50:18 PM PDT 24 170802560 ps
T429 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1627659230 Jul 07 04:50:05 PM PDT 24 Jul 07 04:50:33 PM PDT 24 44184604167 ps
T430 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2805939151 Jul 07 04:49:49 PM PDT 24 Jul 07 04:50:17 PM PDT 24 52236208714 ps
T431 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2723710256 Jul 07 04:49:49 PM PDT 24 Jul 07 04:50:06 PM PDT 24 4904022173 ps
T432 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1895256203 Jul 07 04:49:48 PM PDT 24 Jul 07 04:50:15 PM PDT 24 6494477173 ps
T433 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.264058165 Jul 07 04:49:49 PM PDT 24 Jul 07 04:50:22 PM PDT 24 3586580233 ps
T434 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.714250345 Jul 07 04:50:00 PM PDT 24 Jul 07 04:50:19 PM PDT 24 5232788268 ps
T110 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3834546077 Jul 07 04:49:46 PM PDT 24 Jul 07 04:52:21 PM PDT 24 1001502377 ps
T435 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1320655709 Jul 07 04:50:02 PM PDT 24 Jul 07 04:51:48 PM PDT 24 15848051593 ps
T436 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3351663889 Jul 07 04:49:52 PM PDT 24 Jul 07 04:50:31 PM PDT 24 2548384751 ps
T437 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.889097194 Jul 07 04:49:47 PM PDT 24 Jul 07 04:50:06 PM PDT 24 6491334160 ps
T438 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4279755912 Jul 07 04:49:51 PM PDT 24 Jul 07 04:50:17 PM PDT 24 11124184840 ps
T439 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.4120254014 Jul 07 04:50:00 PM PDT 24 Jul 07 04:50:21 PM PDT 24 2093260607 ps
T440 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2280541442 Jul 07 04:49:51 PM PDT 24 Jul 07 04:50:24 PM PDT 24 4059491363 ps
T86 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.724317074 Jul 07 04:49:55 PM PDT 24 Jul 07 04:50:35 PM PDT 24 704723958 ps
T441 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.694714209 Jul 07 04:50:01 PM PDT 24 Jul 07 04:53:17 PM PDT 24 47108300789 ps
T442 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1101619862 Jul 07 04:49:57 PM PDT 24 Jul 07 04:51:25 PM PDT 24 6822163280 ps
T443 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3402409291 Jul 07 04:49:51 PM PDT 24 Jul 07 04:52:36 PM PDT 24 1530015831 ps
T444 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.807687873 Jul 07 04:49:51 PM PDT 24 Jul 07 04:50:11 PM PDT 24 9159113957 ps
T445 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3361894048 Jul 07 04:49:42 PM PDT 24 Jul 07 04:51:41 PM PDT 24 151366620314 ps
T446 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.165742212 Jul 07 04:50:05 PM PDT 24 Jul 07 04:50:36 PM PDT 24 7676277313 ps
T447 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4236174933 Jul 07 04:49:51 PM PDT 24 Jul 07 04:50:21 PM PDT 24 5545634301 ps
T448 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2043002316 Jul 07 04:49:56 PM PDT 24 Jul 07 04:50:28 PM PDT 24 30121581396 ps
T100 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.523630753 Jul 07 04:50:02 PM PDT 24 Jul 07 04:51:42 PM PDT 24 22970854437 ps
T449 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2079165302 Jul 07 04:50:03 PM PDT 24 Jul 07 04:50:37 PM PDT 24 21057676686 ps
T450 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4209459292 Jul 07 04:49:58 PM PDT 24 Jul 07 04:50:21 PM PDT 24 10152255061 ps
T451 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1595283649 Jul 07 04:49:44 PM PDT 24 Jul 07 04:50:02 PM PDT 24 788634709 ps
T452 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3871720700 Jul 07 04:50:05 PM PDT 24 Jul 07 04:50:29 PM PDT 24 8536426602 ps
T453 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4088787833 Jul 07 04:49:51 PM PDT 24 Jul 07 04:50:19 PM PDT 24 8861107215 ps
T454 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2784953045 Jul 07 04:49:48 PM PDT 24 Jul 07 04:50:19 PM PDT 24 47863500943 ps
T455 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3603449263 Jul 07 04:49:47 PM PDT 24 Jul 07 04:50:11 PM PDT 24 2380708253 ps
T456 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.322728430 Jul 07 04:49:41 PM PDT 24 Jul 07 04:50:04 PM PDT 24 5269667219 ps
T457 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3182424391 Jul 07 04:49:54 PM PDT 24 Jul 07 04:50:11 PM PDT 24 647637095 ps
T458 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1115678619 Jul 07 04:49:56 PM PDT 24 Jul 07 04:50:09 PM PDT 24 2391732931 ps
T459 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2777252758 Jul 07 04:49:51 PM PDT 24 Jul 07 04:50:00 PM PDT 24 2749279552 ps

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2560901106
Short name T2
Test name
Test status
Simulation time 31554106163 ps
CPU time 353.29 seconds
Started Jul 07 04:50:36 PM PDT 24
Finished Jul 07 04:56:30 PM PDT 24
Peak memory 233724 kb
Host smart-25bd2e61-33d9-4033-b36f-03715fbfc620
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560901106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2560901106
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1744838811
Short name T15
Test name
Test status
Simulation time 440770122252 ps
CPU time 4285.47 seconds
Started Jul 07 04:50:46 PM PDT 24
Finished Jul 07 06:02:13 PM PDT 24
Peak memory 252516 kb
Host smart-0e8b3587-c57f-4741-8df9-db23d0070361
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744838811 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.1744838811
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.620379399
Short name T35
Test name
Test status
Simulation time 13873205422 ps
CPU time 299.46 seconds
Started Jul 07 04:50:46 PM PDT 24
Finished Jul 07 04:55:46 PM PDT 24
Peak memory 219332 kb
Host smart-e82c40b7-e91c-4a39-b278-8ee6355db80b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620379399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.620379399
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2002959828
Short name T8
Test name
Test status
Simulation time 4087700607 ps
CPU time 33.89 seconds
Started Jul 07 04:50:58 PM PDT 24
Finished Jul 07 04:51:33 PM PDT 24
Peak memory 214772 kb
Host smart-c4cba4f9-66bf-4616-b0ac-53a815ddfdc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002959828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2002959828
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3496878490
Short name T102
Test name
Test status
Simulation time 7287587047 ps
CPU time 171.73 seconds
Started Jul 07 04:50:03 PM PDT 24
Finished Jul 07 04:52:56 PM PDT 24
Peak memory 214024 kb
Host smart-8af5f2e7-a525-478f-9f7f-f3a730787853
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496878490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3496878490
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3094498417
Short name T1
Test name
Test status
Simulation time 5193878517 ps
CPU time 12.64 seconds
Started Jul 07 04:51:45 PM PDT 24
Finished Jul 07 04:51:58 PM PDT 24
Peak memory 217484 kb
Host smart-2a90c828-8f5f-41ef-b849-6a88ff72c796
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094498417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3094498417
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1874937819
Short name T22
Test name
Test status
Simulation time 14918459968 ps
CPU time 247.72 seconds
Started Jul 07 04:50:08 PM PDT 24
Finished Jul 07 04:54:16 PM PDT 24
Peak memory 238668 kb
Host smart-fcc4dae5-98d2-4325-a462-bb23eceaebdd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874937819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1874937819
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.318639821
Short name T67
Test name
Test status
Simulation time 4556628050 ps
CPU time 38.48 seconds
Started Jul 07 04:50:00 PM PDT 24
Finished Jul 07 04:50:38 PM PDT 24
Peak memory 211560 kb
Host smart-c5832d3a-29c9-4abe-8524-148af0bb8486
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318639821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.318639821
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2106742278
Short name T103
Test name
Test status
Simulation time 2485410207 ps
CPU time 155.78 seconds
Started Jul 07 04:50:00 PM PDT 24
Finished Jul 07 04:52:36 PM PDT 24
Peak memory 213812 kb
Host smart-3a2ed61f-3127-416b-b33b-f45ef463ab66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106742278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2106742278
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.1771989191
Short name T77
Test name
Test status
Simulation time 2474176304 ps
CPU time 41.35 seconds
Started Jul 07 04:51:50 PM PDT 24
Finished Jul 07 04:52:32 PM PDT 24
Peak memory 216448 kb
Host smart-9f40e01b-e3d4-454e-a9ad-8c4e9a136e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771989191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.1771989191
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1444960988
Short name T37
Test name
Test status
Simulation time 11986689969 ps
CPU time 222.1 seconds
Started Jul 07 04:51:05 PM PDT 24
Finished Jul 07 04:54:47 PM PDT 24
Peak memory 230784 kb
Host smart-6a2c1c56-c962-43c2-9eae-cac3024e7957
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444960988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1444960988
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3908518295
Short name T126
Test name
Test status
Simulation time 660326870 ps
CPU time 24.23 seconds
Started Jul 07 04:51:43 PM PDT 24
Finished Jul 07 04:52:07 PM PDT 24
Peak memory 218688 kb
Host smart-15e3a23a-735c-4c71-9138-37e680f537fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908518295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3908518295
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3524796070
Short name T40
Test name
Test status
Simulation time 346119098 ps
CPU time 19.4 seconds
Started Jul 07 04:50:07 PM PDT 24
Finished Jul 07 04:50:27 PM PDT 24
Peak memory 219288 kb
Host smart-9ff8dce3-975b-460e-801f-d8b262a79155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524796070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3524796070
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.1416458707
Short name T14
Test name
Test status
Simulation time 17291633700 ps
CPU time 5856.41 seconds
Started Jul 07 04:50:58 PM PDT 24
Finished Jul 07 06:28:36 PM PDT 24
Peak memory 235720 kb
Host smart-4d6b9b0b-bb4d-4372-b022-24ecf2481932
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416458707 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.1416458707
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.754290023
Short name T79
Test name
Test status
Simulation time 1285227945 ps
CPU time 13.05 seconds
Started Jul 07 04:50:00 PM PDT 24
Finished Jul 07 04:50:13 PM PDT 24
Peak memory 210464 kb
Host smart-1dd808db-518e-4ceb-a765-4fe5334c257c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754290023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.754290023
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3317144659
Short name T109
Test name
Test status
Simulation time 18568301074 ps
CPU time 96.81 seconds
Started Jul 07 04:49:42 PM PDT 24
Finished Jul 07 04:51:19 PM PDT 24
Peak memory 213840 kb
Host smart-63d4ccbd-780f-42c8-a604-aae25e3ce71c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317144659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3317144659
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.82845141
Short name T111
Test name
Test status
Simulation time 2253017219 ps
CPU time 164.18 seconds
Started Jul 07 04:49:57 PM PDT 24
Finished Jul 07 04:52:41 PM PDT 24
Peak memory 213816 kb
Host smart-b685f305-5bc9-44d0-9a53-cea032d7d1db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82845141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_int
g_err.82845141
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.523630753
Short name T100
Test name
Test status
Simulation time 22970854437 ps
CPU time 99.48 seconds
Started Jul 07 04:50:02 PM PDT 24
Finished Jul 07 04:51:42 PM PDT 24
Peak memory 214756 kb
Host smart-64ea7df7-c8bd-427f-bf0c-05037d73f317
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523630753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_pa
ssthru_mem_tl_intg_err.523630753
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.154329268
Short name T18
Test name
Test status
Simulation time 39566974801 ps
CPU time 176.43 seconds
Started Jul 07 04:50:29 PM PDT 24
Finished Jul 07 04:53:26 PM PDT 24
Peak memory 221116 kb
Host smart-d5cb350f-1f4c-47fd-b5e2-ecb0ef239c5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154329268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.154329268
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3799277282
Short name T399
Test name
Test status
Simulation time 6195181672 ps
CPU time 18.34 seconds
Started Jul 07 04:49:42 PM PDT 24
Finished Jul 07 04:50:00 PM PDT 24
Peak memory 211684 kb
Host smart-7b5f1349-01ef-4f89-ab71-a55801d541e4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799277282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3799277282
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2280541442
Short name T440
Test name
Test status
Simulation time 4059491363 ps
CPU time 32.09 seconds
Started Jul 07 04:49:51 PM PDT 24
Finished Jul 07 04:50:24 PM PDT 24
Peak memory 211316 kb
Host smart-07dc8275-3b28-4ddd-a408-03cd71b29ca7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280541442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2280541442
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4018851924
Short name T87
Test name
Test status
Simulation time 1015627670 ps
CPU time 15.18 seconds
Started Jul 07 04:49:43 PM PDT 24
Finished Jul 07 04:49:59 PM PDT 24
Peak memory 211548 kb
Host smart-a8ce4dac-de42-4186-b9f4-a9cee22c9c34
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018851924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.4018851924
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1726438730
Short name T416
Test name
Test status
Simulation time 360399718 ps
CPU time 8.93 seconds
Started Jul 07 04:49:44 PM PDT 24
Finished Jul 07 04:49:53 PM PDT 24
Peak memory 215752 kb
Host smart-8caacb7a-22b7-45ca-bdd7-b1c25b35f526
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726438730 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1726438730
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.528855789
Short name T90
Test name
Test status
Simulation time 40033861465 ps
CPU time 30.66 seconds
Started Jul 07 04:49:46 PM PDT 24
Finished Jul 07 04:50:17 PM PDT 24
Peak memory 212236 kb
Host smart-0422b127-0544-4321-9aac-a025b2101dda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528855789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.528855789
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3292323379
Short name T414
Test name
Test status
Simulation time 1024838847 ps
CPU time 11.48 seconds
Started Jul 07 04:49:43 PM PDT 24
Finished Jul 07 04:49:55 PM PDT 24
Peak memory 210392 kb
Host smart-3913c72f-4037-4252-a79c-f7e72daa72b0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292323379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3292323379
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.226969809
Short name T360
Test name
Test status
Simulation time 172572117 ps
CPU time 8.21 seconds
Started Jul 07 04:49:51 PM PDT 24
Finished Jul 07 04:50:01 PM PDT 24
Peak memory 210200 kb
Host smart-19080616-a4e5-4055-ba6b-d142e3c772db
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226969809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
226969809
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.514573537
Short name T394
Test name
Test status
Simulation time 689782846 ps
CPU time 37.96 seconds
Started Jul 07 04:49:51 PM PDT 24
Finished Jul 07 04:50:30 PM PDT 24
Peak memory 213648 kb
Host smart-09ab61ac-89aa-4227-bb72-8b58280b2553
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514573537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.514573537
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1710021610
Short name T409
Test name
Test status
Simulation time 2632561023 ps
CPU time 13.13 seconds
Started Jul 07 04:49:48 PM PDT 24
Finished Jul 07 04:50:02 PM PDT 24
Peak memory 211192 kb
Host smart-945e885e-f21a-4945-a34d-7811f5811d3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710021610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1710021610
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4088787833
Short name T453
Test name
Test status
Simulation time 8861107215 ps
CPU time 27.04 seconds
Started Jul 07 04:49:51 PM PDT 24
Finished Jul 07 04:50:19 PM PDT 24
Peak memory 217768 kb
Host smart-3736f512-16cb-430f-8aeb-2d1cadc76636
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088787833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.4088787833
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1569122747
Short name T105
Test name
Test status
Simulation time 7649328487 ps
CPU time 100.98 seconds
Started Jul 07 04:49:45 PM PDT 24
Finished Jul 07 04:51:26 PM PDT 24
Peak memory 212464 kb
Host smart-63a9397c-9bf3-403f-94e0-cf6b99d8a3df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569122747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1569122747
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2777252758
Short name T459
Test name
Test status
Simulation time 2749279552 ps
CPU time 8.45 seconds
Started Jul 07 04:49:51 PM PDT 24
Finished Jul 07 04:50:00 PM PDT 24
Peak memory 210684 kb
Host smart-afd83831-5389-4a4a-b1b7-bd2866c1a495
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777252758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2777252758
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.61324839
Short name T396
Test name
Test status
Simulation time 1227886702 ps
CPU time 16.47 seconds
Started Jul 07 04:49:42 PM PDT 24
Finished Jul 07 04:49:59 PM PDT 24
Peak memory 210588 kb
Host smart-9270185c-d6ad-462d-8628-822a79a47540
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61324839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_ba
sh.61324839
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3763840226
Short name T427
Test name
Test status
Simulation time 3091506589 ps
CPU time 16.37 seconds
Started Jul 07 04:49:41 PM PDT 24
Finished Jul 07 04:49:58 PM PDT 24
Peak memory 210576 kb
Host smart-78435172-2358-4593-b3fb-7c001dc71026
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763840226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3763840226
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.464719259
Short name T408
Test name
Test status
Simulation time 4138418583 ps
CPU time 13.79 seconds
Started Jul 07 04:49:45 PM PDT 24
Finished Jul 07 04:49:59 PM PDT 24
Peak memory 213596 kb
Host smart-2528561e-e5b6-4ea1-9632-61df98381f35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464719259 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.464719259
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1651713172
Short name T426
Test name
Test status
Simulation time 43075404925 ps
CPU time 23.3 seconds
Started Jul 07 04:49:44 PM PDT 24
Finished Jul 07 04:50:08 PM PDT 24
Peak memory 211772 kb
Host smart-ffa2ce50-343d-4fe9-8e42-b41e6cd7ec7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651713172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1651713172
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.322728430
Short name T456
Test name
Test status
Simulation time 5269667219 ps
CPU time 23.03 seconds
Started Jul 07 04:49:41 PM PDT 24
Finished Jul 07 04:50:04 PM PDT 24
Peak memory 210828 kb
Host smart-9c1ea24e-7da2-4dd8-88c4-9941a59f3e82
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322728430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.322728430
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2357828184
Short name T372
Test name
Test status
Simulation time 3473394942 ps
CPU time 27.31 seconds
Started Jul 07 04:49:50 PM PDT 24
Finished Jul 07 04:50:18 PM PDT 24
Peak memory 210500 kb
Host smart-8a392cd7-4e9d-455e-a8cf-351d775e6c15
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357828184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2357828184
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3361894048
Short name T445
Test name
Test status
Simulation time 151366620314 ps
CPU time 118.9 seconds
Started Jul 07 04:49:42 PM PDT 24
Finished Jul 07 04:51:41 PM PDT 24
Peak memory 214740 kb
Host smart-46f6e51e-4b61-4c5d-9873-8efe19e6980b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361894048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3361894048
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1595283649
Short name T451
Test name
Test status
Simulation time 788634709 ps
CPU time 17.3 seconds
Started Jul 07 04:49:44 PM PDT 24
Finished Jul 07 04:50:02 PM PDT 24
Peak memory 212196 kb
Host smart-216ad19a-5db0-4e08-b338-e193c02e036b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595283649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1595283649
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3112416814
Short name T392
Test name
Test status
Simulation time 1367684754 ps
CPU time 20.08 seconds
Started Jul 07 04:49:42 PM PDT 24
Finished Jul 07 04:50:02 PM PDT 24
Peak memory 218196 kb
Host smart-06a56699-4c91-4718-b44a-290f526a944c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112416814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3112416814
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.714250345
Short name T434
Test name
Test status
Simulation time 5232788268 ps
CPU time 18.25 seconds
Started Jul 07 04:50:00 PM PDT 24
Finished Jul 07 04:50:19 PM PDT 24
Peak memory 216832 kb
Host smart-f4c15f0d-e0a2-410d-bd43-d33caef3e210
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714250345 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.714250345
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3889024516
Short name T380
Test name
Test status
Simulation time 15375237555 ps
CPU time 16.18 seconds
Started Jul 07 04:50:03 PM PDT 24
Finished Jul 07 04:50:20 PM PDT 24
Peak memory 211848 kb
Host smart-38b13878-e873-49f4-9bb2-28d14395f79e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889024516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3889024516
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.724317074
Short name T86
Test name
Test status
Simulation time 704723958 ps
CPU time 39.23 seconds
Started Jul 07 04:49:55 PM PDT 24
Finished Jul 07 04:50:35 PM PDT 24
Peak memory 213636 kb
Host smart-92a10300-ac5c-4c01-8b39-50029a795ad8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724317074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.724317074
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.4120254014
Short name T439
Test name
Test status
Simulation time 2093260607 ps
CPU time 20.5 seconds
Started Jul 07 04:50:00 PM PDT 24
Finished Jul 07 04:50:21 PM PDT 24
Peak memory 212096 kb
Host smart-7c14d6ac-4020-4ddf-b5ea-29b374adbe4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120254014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.4120254014
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.4178253005
Short name T375
Test name
Test status
Simulation time 4777332299 ps
CPU time 19.53 seconds
Started Jul 07 04:49:57 PM PDT 24
Finished Jul 07 04:50:17 PM PDT 24
Peak memory 218472 kb
Host smart-a721953d-3e36-4475-a938-f81d17c999d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178253005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.4178253005
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2505412544
Short name T59
Test name
Test status
Simulation time 274679344 ps
CPU time 80.5 seconds
Started Jul 07 04:50:01 PM PDT 24
Finished Jul 07 04:51:22 PM PDT 24
Peak memory 213596 kb
Host smart-a72b34b7-442c-43f2-9058-4612a20703f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505412544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2505412544
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3167244425
Short name T407
Test name
Test status
Simulation time 2557057147 ps
CPU time 23.88 seconds
Started Jul 07 04:49:54 PM PDT 24
Finished Jul 07 04:50:18 PM PDT 24
Peak memory 216952 kb
Host smart-55342701-5ab6-4573-9856-c264386ba543
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167244425 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3167244425
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3582491648
Short name T390
Test name
Test status
Simulation time 34224520299 ps
CPU time 87.01 seconds
Started Jul 07 04:50:03 PM PDT 24
Finished Jul 07 04:51:31 PM PDT 24
Peak memory 213592 kb
Host smart-931b0348-c91a-4cdf-b817-c72223aef1ab
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582491648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3582491648
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3534368025
Short name T406
Test name
Test status
Simulation time 184041547 ps
CPU time 11.98 seconds
Started Jul 07 04:49:56 PM PDT 24
Finished Jul 07 04:50:08 PM PDT 24
Peak memory 212424 kb
Host smart-858a983b-1c1a-4a0a-b46d-4e5cf319ad04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534368025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3534368025
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2043002316
Short name T448
Test name
Test status
Simulation time 30121581396 ps
CPU time 31.7 seconds
Started Jul 07 04:49:56 PM PDT 24
Finished Jul 07 04:50:28 PM PDT 24
Peak memory 218880 kb
Host smart-1d40a02c-ae37-4077-9c26-d0f48994c58c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043002316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2043002316
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3912661378
Short name T373
Test name
Test status
Simulation time 3622817970 ps
CPU time 29.35 seconds
Started Jul 07 04:49:58 PM PDT 24
Finished Jul 07 04:50:27 PM PDT 24
Peak memory 217292 kb
Host smart-ae8c3a18-fb7d-46bf-ba18-3ae79260139b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912661378 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3912661378
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3739408451
Short name T95
Test name
Test status
Simulation time 3444188755 ps
CPU time 29.16 seconds
Started Jul 07 04:50:00 PM PDT 24
Finished Jul 07 04:50:30 PM PDT 24
Peak memory 211820 kb
Host smart-3ec9db54-8d5a-457e-929c-dddc6cb58780
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739408451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3739408451
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3264604712
Short name T382
Test name
Test status
Simulation time 7481099421 ps
CPU time 28.17 seconds
Started Jul 07 04:50:00 PM PDT 24
Finished Jul 07 04:50:29 PM PDT 24
Peak memory 212560 kb
Host smart-5c7d1243-40ba-47aa-82ff-326b90b0dea0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264604712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3264604712
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3237021958
Short name T410
Test name
Test status
Simulation time 167754901 ps
CPU time 13.28 seconds
Started Jul 07 04:49:54 PM PDT 24
Finished Jul 07 04:50:08 PM PDT 24
Peak memory 217268 kb
Host smart-87662ec9-3428-4bcc-9835-5af0a844d312
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237021958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3237021958
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1101619862
Short name T442
Test name
Test status
Simulation time 6822163280 ps
CPU time 88.03 seconds
Started Jul 07 04:49:57 PM PDT 24
Finished Jul 07 04:51:25 PM PDT 24
Peak memory 213804 kb
Host smart-c384393d-7964-4d1b-814d-ea5d7b92661c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101619862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1101619862
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2489724
Short name T365
Test name
Test status
Simulation time 4191755019 ps
CPU time 15.31 seconds
Started Jul 07 04:50:03 PM PDT 24
Finished Jul 07 04:50:18 PM PDT 24
Peak memory 216656 kb
Host smart-531f464f-a9a9-49b8-9205-30e24059f985
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489724 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2489724
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3230011720
Short name T419
Test name
Test status
Simulation time 4079941772 ps
CPU time 15.49 seconds
Started Jul 07 04:50:01 PM PDT 24
Finished Jul 07 04:50:17 PM PDT 24
Peak memory 210932 kb
Host smart-075c87e1-e887-4384-b478-eaf426cbcf9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230011720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3230011720
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.4071302983
Short name T101
Test name
Test status
Simulation time 4127650108 ps
CPU time 56.05 seconds
Started Jul 07 04:50:00 PM PDT 24
Finished Jul 07 04:50:56 PM PDT 24
Peak memory 214732 kb
Host smart-8ae26978-5c93-416d-8741-fe648075d12c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071302983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.4071302983
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3618924687
Short name T93
Test name
Test status
Simulation time 5590169810 ps
CPU time 24.9 seconds
Started Jul 07 04:50:03 PM PDT 24
Finished Jul 07 04:50:28 PM PDT 24
Peak memory 211952 kb
Host smart-160cfd7e-cf81-4095-94fa-46a788741bd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618924687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3618924687
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3911698164
Short name T377
Test name
Test status
Simulation time 4182536775 ps
CPU time 39.42 seconds
Started Jul 07 04:50:02 PM PDT 24
Finished Jul 07 04:50:42 PM PDT 24
Peak memory 218428 kb
Host smart-0208fa2b-3faf-4b39-ad0e-6e240b1d4e22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911698164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3911698164
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3457475805
Short name T362
Test name
Test status
Simulation time 1451483359 ps
CPU time 17.41 seconds
Started Jul 07 04:50:01 PM PDT 24
Finished Jul 07 04:50:19 PM PDT 24
Peak memory 213416 kb
Host smart-8a328364-a921-451f-b8f9-d444c563ca6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457475805 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3457475805
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3569859531
Short name T61
Test name
Test status
Simulation time 4501939334 ps
CPU time 21.84 seconds
Started Jul 07 04:50:01 PM PDT 24
Finished Jul 07 04:50:23 PM PDT 24
Peak memory 211756 kb
Host smart-33c1a683-4dbb-41ce-b47a-d5e7d72d5879
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569859531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3569859531
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1775172331
Short name T85
Test name
Test status
Simulation time 14136106736 ps
CPU time 121.15 seconds
Started Jul 07 04:50:03 PM PDT 24
Finished Jul 07 04:52:04 PM PDT 24
Peak memory 213768 kb
Host smart-8861734f-8e69-4be9-831e-30c010985759
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775172331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1775172331
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2768127104
Short name T404
Test name
Test status
Simulation time 21102378646 ps
CPU time 31.64 seconds
Started Jul 07 04:50:00 PM PDT 24
Finished Jul 07 04:50:32 PM PDT 24
Peak memory 212400 kb
Host smart-e7f497ce-fc8d-4ce5-aac2-b87238172a1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768127104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2768127104
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3374976190
Short name T398
Test name
Test status
Simulation time 4030854151 ps
CPU time 26.6 seconds
Started Jul 07 04:50:05 PM PDT 24
Finished Jul 07 04:50:32 PM PDT 24
Peak memory 218344 kb
Host smart-99092a3a-db38-4021-a090-86168b3ffc6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374976190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3374976190
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1788611068
Short name T57
Test name
Test status
Simulation time 4295543128 ps
CPU time 169.94 seconds
Started Jul 07 04:50:01 PM PDT 24
Finished Jul 07 04:52:52 PM PDT 24
Peak memory 213772 kb
Host smart-ccc9a77f-acef-4970-87cf-eaffc0dc48f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788611068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1788611068
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2317011860
Short name T369
Test name
Test status
Simulation time 2992242492 ps
CPU time 14.45 seconds
Started Jul 07 04:49:59 PM PDT 24
Finished Jul 07 04:50:14 PM PDT 24
Peak memory 217424 kb
Host smart-f13007c3-982b-4bea-a338-fa4aea0361b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317011860 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2317011860
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2193909900
Short name T371
Test name
Test status
Simulation time 2856288336 ps
CPU time 17.76 seconds
Started Jul 07 04:50:03 PM PDT 24
Finished Jul 07 04:50:22 PM PDT 24
Peak memory 210564 kb
Host smart-fa941142-027e-4a6d-ae8c-6235ee3cb391
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193909900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2193909900
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.694714209
Short name T441
Test name
Test status
Simulation time 47108300789 ps
CPU time 195.74 seconds
Started Jul 07 04:50:01 PM PDT 24
Finished Jul 07 04:53:17 PM PDT 24
Peak memory 214820 kb
Host smart-de614681-5410-4eea-afa8-e03ff6afb720
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694714209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.694714209
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.433888779
Short name T417
Test name
Test status
Simulation time 1743277767 ps
CPU time 19.23 seconds
Started Jul 07 04:50:02 PM PDT 24
Finished Jul 07 04:50:21 PM PDT 24
Peak memory 212120 kb
Host smart-bdbbbd67-cbcf-456c-b70e-cf8199dd4a3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433888779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.433888779
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1417693139
Short name T401
Test name
Test status
Simulation time 25511800409 ps
CPU time 24.78 seconds
Started Jul 07 04:50:02 PM PDT 24
Finished Jul 07 04:50:27 PM PDT 24
Peak memory 218396 kb
Host smart-a97c6fe5-75ba-40f6-a7de-10a582861fb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417693139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1417693139
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.217748302
Short name T402
Test name
Test status
Simulation time 17944186304 ps
CPU time 32.12 seconds
Started Jul 07 04:50:04 PM PDT 24
Finished Jul 07 04:50:37 PM PDT 24
Peak memory 214036 kb
Host smart-bb2b8ca7-818b-4db7-9460-cfd0c69c7aa4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217748302 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.217748302
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2323126360
Short name T71
Test name
Test status
Simulation time 6535567972 ps
CPU time 27.97 seconds
Started Jul 07 04:50:02 PM PDT 24
Finished Jul 07 04:50:30 PM PDT 24
Peak memory 211964 kb
Host smart-91f14a94-e89b-4a81-a5a1-8833f5f56553
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323126360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2323126360
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1320655709
Short name T435
Test name
Test status
Simulation time 15848051593 ps
CPU time 105.73 seconds
Started Jul 07 04:50:02 PM PDT 24
Finished Jul 07 04:51:48 PM PDT 24
Peak memory 211380 kb
Host smart-a6d048d8-5b44-467d-8d66-1701b3c86283
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320655709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1320655709
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.165742212
Short name T446
Test name
Test status
Simulation time 7676277313 ps
CPU time 31.14 seconds
Started Jul 07 04:50:05 PM PDT 24
Finished Jul 07 04:50:36 PM PDT 24
Peak memory 212616 kb
Host smart-8f68d4b6-a1d6-4681-9c82-0158a57950b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165742212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.165742212
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1914928955
Short name T397
Test name
Test status
Simulation time 937546335 ps
CPU time 19.75 seconds
Started Jul 07 04:50:05 PM PDT 24
Finished Jul 07 04:50:25 PM PDT 24
Peak memory 217212 kb
Host smart-13e32fa8-5911-462b-ba04-8dfedfab97b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914928955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1914928955
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3665991745
Short name T107
Test name
Test status
Simulation time 9716987715 ps
CPU time 169.11 seconds
Started Jul 07 04:50:01 PM PDT 24
Finished Jul 07 04:52:51 PM PDT 24
Peak memory 214284 kb
Host smart-e0e45d57-1f13-47b7-a61a-c4ebdf854e6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665991745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3665991745
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.547413399
Short name T381
Test name
Test status
Simulation time 9251403340 ps
CPU time 22.33 seconds
Started Jul 07 04:50:04 PM PDT 24
Finished Jul 07 04:50:27 PM PDT 24
Peak memory 214492 kb
Host smart-4b4fa08a-828a-4426-af6f-a9e486529e1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547413399 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.547413399
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3901484418
Short name T68
Test name
Test status
Simulation time 8029612326 ps
CPU time 30.51 seconds
Started Jul 07 04:50:05 PM PDT 24
Finished Jul 07 04:50:36 PM PDT 24
Peak memory 212012 kb
Host smart-a86f4a7e-93f9-4470-b54e-236d7e0733b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901484418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3901484418
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2680459477
Short name T425
Test name
Test status
Simulation time 8748363146 ps
CPU time 111.88 seconds
Started Jul 07 04:50:03 PM PDT 24
Finished Jul 07 04:51:55 PM PDT 24
Peak memory 215452 kb
Host smart-620a4313-abaf-4fd1-b6e5-b828dfd9c7b2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680459477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2680459477
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1022969488
Short name T91
Test name
Test status
Simulation time 4791186187 ps
CPU time 22.86 seconds
Started Jul 07 04:50:04 PM PDT 24
Finished Jul 07 04:50:28 PM PDT 24
Peak memory 212668 kb
Host smart-cbcffcbf-2105-49f9-a15b-70c2601ff351
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022969488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1022969488
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1627659230
Short name T429
Test name
Test status
Simulation time 44184604167 ps
CPU time 27.85 seconds
Started Jul 07 04:50:05 PM PDT 24
Finished Jul 07 04:50:33 PM PDT 24
Peak memory 218512 kb
Host smart-b66d28c4-5f10-44e0-8842-6ad49fe5a54b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627659230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1627659230
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2260176712
Short name T112
Test name
Test status
Simulation time 8384919382 ps
CPU time 175.07 seconds
Started Jul 07 04:50:04 PM PDT 24
Finished Jul 07 04:53:00 PM PDT 24
Peak memory 214180 kb
Host smart-ac595af1-7e36-463a-bffb-849085e15b14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260176712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2260176712
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2349791197
Short name T379
Test name
Test status
Simulation time 1032819341 ps
CPU time 14.75 seconds
Started Jul 07 04:50:03 PM PDT 24
Finished Jul 07 04:50:18 PM PDT 24
Peak memory 214012 kb
Host smart-b78b3d82-6ee5-475e-b0a5-08a1beb8b15d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349791197 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2349791197
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.241948768
Short name T387
Test name
Test status
Simulation time 661616040 ps
CPU time 8.32 seconds
Started Jul 07 04:50:03 PM PDT 24
Finished Jul 07 04:50:12 PM PDT 24
Peak memory 210764 kb
Host smart-19526a56-e47b-47e5-9330-5a638eaff2f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241948768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.241948768
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.909636226
Short name T92
Test name
Test status
Simulation time 3781057295 ps
CPU time 29.4 seconds
Started Jul 07 04:50:04 PM PDT 24
Finished Jul 07 04:50:34 PM PDT 24
Peak memory 212320 kb
Host smart-9897134c-88f1-4c52-adca-a04412c33d83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909636226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.909636226
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2024093458
Short name T428
Test name
Test status
Simulation time 170802560 ps
CPU time 11.78 seconds
Started Jul 07 04:50:06 PM PDT 24
Finished Jul 07 04:50:18 PM PDT 24
Peak memory 216240 kb
Host smart-38769ad8-6bf5-49e9-8327-8df98a211265
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024093458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2024093458
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1347237523
Short name T393
Test name
Test status
Simulation time 5301871215 ps
CPU time 158.43 seconds
Started Jul 07 04:50:04 PM PDT 24
Finished Jul 07 04:52:43 PM PDT 24
Peak memory 214220 kb
Host smart-11a5b24a-3638-4450-85e8-4a4270fcccc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347237523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1347237523
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3871720700
Short name T452
Test name
Test status
Simulation time 8536426602 ps
CPU time 23.15 seconds
Started Jul 07 04:50:05 PM PDT 24
Finished Jul 07 04:50:29 PM PDT 24
Peak memory 217752 kb
Host smart-81660808-8cde-45bf-ac24-90fe796002e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871720700 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3871720700
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.955651321
Short name T72
Test name
Test status
Simulation time 2084505159 ps
CPU time 21.05 seconds
Started Jul 07 04:50:04 PM PDT 24
Finished Jul 07 04:50:26 PM PDT 24
Peak memory 211012 kb
Host smart-330a14b3-ef53-4174-a494-cbefc5235826
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955651321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.955651321
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3860420575
Short name T69
Test name
Test status
Simulation time 4229546379 ps
CPU time 44.74 seconds
Started Jul 07 04:50:04 PM PDT 24
Finished Jul 07 04:50:49 PM PDT 24
Peak memory 213652 kb
Host smart-3d7d99eb-c2e4-4efb-a7ca-1754da8f7826
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860420575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3860420575
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.4070740616
Short name T89
Test name
Test status
Simulation time 852538448 ps
CPU time 14.25 seconds
Started Jul 07 04:50:04 PM PDT 24
Finished Jul 07 04:50:19 PM PDT 24
Peak memory 210852 kb
Host smart-b3114ef4-1c12-4ab2-bfa8-92f3b25c9ca5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070740616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.4070740616
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2079165302
Short name T449
Test name
Test status
Simulation time 21057676686 ps
CPU time 33.42 seconds
Started Jul 07 04:50:03 PM PDT 24
Finished Jul 07 04:50:37 PM PDT 24
Peak memory 218564 kb
Host smart-8b6c766a-2914-4f88-8360-a4b02682df7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079165302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2079165302
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3529346588
Short name T106
Test name
Test status
Simulation time 471635187 ps
CPU time 80.38 seconds
Started Jul 07 04:50:04 PM PDT 24
Finished Jul 07 04:51:25 PM PDT 24
Peak memory 213536 kb
Host smart-337983bd-4de8-4c71-a980-c5f5db1a8cc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529346588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3529346588
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.569990906
Short name T83
Test name
Test status
Simulation time 16371837987 ps
CPU time 33.04 seconds
Started Jul 07 04:49:48 PM PDT 24
Finished Jul 07 04:50:21 PM PDT 24
Peak memory 211872 kb
Host smart-1536c60e-c855-44d8-8c6b-800fe6f4b829
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569990906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.569990906
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2805939151
Short name T430
Test name
Test status
Simulation time 52236208714 ps
CPU time 26.88 seconds
Started Jul 07 04:49:49 PM PDT 24
Finished Jul 07 04:50:17 PM PDT 24
Peak memory 211924 kb
Host smart-e4eaf7b3-25dd-44df-a60c-c58935368d75
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805939151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2805939151
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3716821067
Short name T422
Test name
Test status
Simulation time 38327628780 ps
CPU time 30.61 seconds
Started Jul 07 04:49:46 PM PDT 24
Finished Jul 07 04:50:17 PM PDT 24
Peak memory 211012 kb
Host smart-373ca06e-8da6-4975-ac86-aa2955fa5c31
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716821067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3716821067
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4249707446
Short name T391
Test name
Test status
Simulation time 366301820 ps
CPU time 9.21 seconds
Started Jul 07 04:49:49 PM PDT 24
Finished Jul 07 04:49:59 PM PDT 24
Peak memory 216556 kb
Host smart-30d95de4-d762-47d3-bdad-fed23a95ec14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249707446 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.4249707446
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3235132472
Short name T363
Test name
Test status
Simulation time 19255304825 ps
CPU time 25.64 seconds
Started Jul 07 04:49:45 PM PDT 24
Finished Jul 07 04:50:11 PM PDT 24
Peak memory 212232 kb
Host smart-7ab6b674-993d-40ce-9c2d-f5d5886c9b7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235132472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3235132472
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.17510877
Short name T405
Test name
Test status
Simulation time 1357929979 ps
CPU time 17.4 seconds
Started Jul 07 04:49:50 PM PDT 24
Finished Jul 07 04:50:08 PM PDT 24
Peak memory 210448 kb
Host smart-28d18117-6350-4917-924b-3ed4d3ad7bf5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17510877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_
mem_partial_access.17510877
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.889097194
Short name T437
Test name
Test status
Simulation time 6491334160 ps
CPU time 18.19 seconds
Started Jul 07 04:49:47 PM PDT 24
Finished Jul 07 04:50:06 PM PDT 24
Peak memory 210788 kb
Host smart-aa759b74-db52-4c39-adcd-19c81ba7b5e1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889097194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
889097194
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1358363227
Short name T364
Test name
Test status
Simulation time 1037923154 ps
CPU time 58.08 seconds
Started Jul 07 04:49:44 PM PDT 24
Finished Jul 07 04:50:42 PM PDT 24
Peak memory 214972 kb
Host smart-8e07fba3-9ea4-4b8c-9a60-8d1ed63a1b8b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358363227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1358363227
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1014500964
Short name T70
Test name
Test status
Simulation time 6912280503 ps
CPU time 22.83 seconds
Started Jul 07 04:49:48 PM PDT 24
Finished Jul 07 04:50:11 PM PDT 24
Peak memory 212368 kb
Host smart-551a2135-cb70-498e-8fa6-a4778685034d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014500964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1014500964
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2300254411
Short name T403
Test name
Test status
Simulation time 12370626792 ps
CPU time 30.74 seconds
Started Jul 07 04:49:44 PM PDT 24
Finished Jul 07 04:50:15 PM PDT 24
Peak memory 217484 kb
Host smart-ca249740-2cce-4761-922a-a995e60662fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300254411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2300254411
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2801353033
Short name T361
Test name
Test status
Simulation time 283255223 ps
CPU time 83.68 seconds
Started Jul 07 04:49:48 PM PDT 24
Finished Jul 07 04:51:12 PM PDT 24
Peak memory 212564 kb
Host smart-53673918-4fbf-4fc8-97cd-b2f0062a4699
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801353033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2801353033
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.64032982
Short name T84
Test name
Test status
Simulation time 3950919874 ps
CPU time 32.55 seconds
Started Jul 07 04:49:49 PM PDT 24
Finished Jul 07 04:50:22 PM PDT 24
Peak memory 211592 kb
Host smart-417114c1-84e6-452b-9f9c-ab092dd516fb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64032982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_aliasi
ng.64032982
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2392563371
Short name T383
Test name
Test status
Simulation time 7814959670 ps
CPU time 21.7 seconds
Started Jul 07 04:49:46 PM PDT 24
Finished Jul 07 04:50:08 PM PDT 24
Peak memory 212164 kb
Host smart-f63c5d84-3c6b-4d9c-a293-4e87632fe0d1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392563371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2392563371
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.394609878
Short name T400
Test name
Test status
Simulation time 11282846322 ps
CPU time 28.74 seconds
Started Jul 07 04:49:49 PM PDT 24
Finished Jul 07 04:50:18 PM PDT 24
Peak memory 212080 kb
Host smart-1ec19cd2-b082-4c64-ab97-ed4e0fe46d25
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394609878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.394609878
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1292140828
Short name T359
Test name
Test status
Simulation time 2064829278 ps
CPU time 21.86 seconds
Started Jul 07 04:49:47 PM PDT 24
Finished Jul 07 04:50:09 PM PDT 24
Peak memory 217704 kb
Host smart-850fa295-eff1-4eb2-a6f7-e26c2131c8d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292140828 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1292140828
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4071083593
Short name T384
Test name
Test status
Simulation time 1910215162 ps
CPU time 18.88 seconds
Started Jul 07 04:49:50 PM PDT 24
Finished Jul 07 04:50:09 PM PDT 24
Peak memory 211136 kb
Host smart-b51cd029-6707-4995-a3a6-189a930904d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071083593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.4071083593
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.852547773
Short name T411
Test name
Test status
Simulation time 2045134207 ps
CPU time 20.68 seconds
Started Jul 07 04:49:45 PM PDT 24
Finished Jul 07 04:50:06 PM PDT 24
Peak memory 210448 kb
Host smart-319ae3ac-217f-4732-bb8b-1bdc75be536f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852547773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.852547773
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3439614905
Short name T378
Test name
Test status
Simulation time 3625337982 ps
CPU time 29.33 seconds
Started Jul 07 04:49:48 PM PDT 24
Finished Jul 07 04:50:18 PM PDT 24
Peak memory 210528 kb
Host smart-59686f8a-19b7-4258-b4a3-a269622da486
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439614905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.3439614905
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.710992131
Short name T74
Test name
Test status
Simulation time 27186233412 ps
CPU time 140.76 seconds
Started Jul 07 04:49:48 PM PDT 24
Finished Jul 07 04:52:09 PM PDT 24
Peak memory 214952 kb
Host smart-031a85b1-31fe-477b-9e68-b53f758adbde
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710992131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.710992131
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.264058165
Short name T433
Test name
Test status
Simulation time 3586580233 ps
CPU time 32.07 seconds
Started Jul 07 04:49:49 PM PDT 24
Finished Jul 07 04:50:22 PM PDT 24
Peak memory 212404 kb
Host smart-a785d084-c5c8-4bbb-84e0-91f1cd369ac2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264058165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.264058165
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2784953045
Short name T454
Test name
Test status
Simulation time 47863500943 ps
CPU time 30.25 seconds
Started Jul 07 04:49:48 PM PDT 24
Finished Jul 07 04:50:19 PM PDT 24
Peak memory 218600 kb
Host smart-e5119e28-8339-4a5b-abd7-269c4300621f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784953045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2784953045
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3834546077
Short name T110
Test name
Test status
Simulation time 1001502377 ps
CPU time 154.17 seconds
Started Jul 07 04:49:46 PM PDT 24
Finished Jul 07 04:52:21 PM PDT 24
Peak memory 213840 kb
Host smart-7ae084e5-ebd8-49e8-b6e6-11723b04f289
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834546077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3834546077
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2723710256
Short name T431
Test name
Test status
Simulation time 4904022173 ps
CPU time 16.48 seconds
Started Jul 07 04:49:49 PM PDT 24
Finished Jul 07 04:50:06 PM PDT 24
Peak memory 211580 kb
Host smart-12d05c15-7a2f-415a-b884-aa408d24825c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723710256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2723710256
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3939689075
Short name T395
Test name
Test status
Simulation time 293267447 ps
CPU time 10.38 seconds
Started Jul 07 04:49:50 PM PDT 24
Finished Jul 07 04:50:01 PM PDT 24
Peak memory 210576 kb
Host smart-4f05ceec-79aa-4b6e-9516-b20f187ba5c6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939689075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3939689075
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1730623704
Short name T73
Test name
Test status
Simulation time 5740713134 ps
CPU time 22.03 seconds
Started Jul 07 04:49:48 PM PDT 24
Finished Jul 07 04:50:11 PM PDT 24
Peak memory 211804 kb
Host smart-ec7020d9-8292-45fb-96ab-d595b708bf63
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730623704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1730623704
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1245604580
Short name T413
Test name
Test status
Simulation time 15747710666 ps
CPU time 32.58 seconds
Started Jul 07 04:49:50 PM PDT 24
Finished Jul 07 04:50:23 PM PDT 24
Peak memory 214224 kb
Host smart-23a08e5c-be73-4733-b433-51aa698e89a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245604580 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1245604580
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.4183210493
Short name T374
Test name
Test status
Simulation time 2994489528 ps
CPU time 25.15 seconds
Started Jul 07 04:49:47 PM PDT 24
Finished Jul 07 04:50:13 PM PDT 24
Peak memory 212136 kb
Host smart-529ce619-5444-4e52-a5c8-fd7378c3983d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183210493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.4183210493
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3603449263
Short name T455
Test name
Test status
Simulation time 2380708253 ps
CPU time 23.02 seconds
Started Jul 07 04:49:47 PM PDT 24
Finished Jul 07 04:50:11 PM PDT 24
Peak memory 210504 kb
Host smart-4d882d20-d433-45ce-898f-3f99827a3f8d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603449263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3603449263
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2671265604
Short name T415
Test name
Test status
Simulation time 1183789171 ps
CPU time 16.06 seconds
Started Jul 07 04:49:49 PM PDT 24
Finished Jul 07 04:50:06 PM PDT 24
Peak memory 210904 kb
Host smart-c7239860-5924-47ff-ad45-eae5d33ab4f5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671265604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2671265604
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2256862966
Short name T82
Test name
Test status
Simulation time 11034963005 ps
CPU time 55.88 seconds
Started Jul 07 04:49:50 PM PDT 24
Finished Jul 07 04:50:47 PM PDT 24
Peak memory 213696 kb
Host smart-f79e6e4f-48f6-4fbb-b21f-fc5dd66ee035
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256862966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.2256862966
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1895256203
Short name T432
Test name
Test status
Simulation time 6494477173 ps
CPU time 26.79 seconds
Started Jul 07 04:49:48 PM PDT 24
Finished Jul 07 04:50:15 PM PDT 24
Peak memory 212284 kb
Host smart-26888ec5-9095-4436-b705-d397b7a92260
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895256203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1895256203
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3422461330
Short name T367
Test name
Test status
Simulation time 7605045641 ps
CPU time 25.69 seconds
Started Jul 07 04:49:48 PM PDT 24
Finished Jul 07 04:50:13 PM PDT 24
Peak memory 218852 kb
Host smart-2d747ef3-193a-41dc-a458-4a97742e5b21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422461330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3422461330
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2752935447
Short name T104
Test name
Test status
Simulation time 2658716843 ps
CPU time 95.21 seconds
Started Jul 07 04:49:47 PM PDT 24
Finished Jul 07 04:51:22 PM PDT 24
Peak memory 213488 kb
Host smart-ef030de6-0d73-4ffe-8282-3001d2a7bdc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752935447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2752935447
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3935952747
Short name T385
Test name
Test status
Simulation time 586850049 ps
CPU time 9.32 seconds
Started Jul 07 04:49:53 PM PDT 24
Finished Jul 07 04:50:03 PM PDT 24
Peak memory 218856 kb
Host smart-1c06e8d8-2752-4fce-a3d9-0fd2a3123118
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935952747 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3935952747
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.177059166
Short name T62
Test name
Test status
Simulation time 970978771 ps
CPU time 8.42 seconds
Started Jul 07 04:49:51 PM PDT 24
Finished Jul 07 04:50:01 PM PDT 24
Peak memory 210896 kb
Host smart-b81f42e6-4598-4f52-bd72-c5559ec990b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177059166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.177059166
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4047948961
Short name T88
Test name
Test status
Simulation time 1068861630 ps
CPU time 56.94 seconds
Started Jul 07 04:49:51 PM PDT 24
Finished Jul 07 04:50:49 PM PDT 24
Peak memory 214828 kb
Host smart-b2944808-433d-4c38-96b6-7af89ee8851e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047948961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.4047948961
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2202371487
Short name T412
Test name
Test status
Simulation time 2493711898 ps
CPU time 25.65 seconds
Started Jul 07 04:49:51 PM PDT 24
Finished Jul 07 04:50:18 PM PDT 24
Peak memory 212300 kb
Host smart-8ff24cfe-ac0b-4b07-abdc-f2a559ad4460
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202371487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2202371487
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2865295105
Short name T420
Test name
Test status
Simulation time 916303575 ps
CPU time 14.18 seconds
Started Jul 07 04:49:50 PM PDT 24
Finished Jul 07 04:50:05 PM PDT 24
Peak memory 217404 kb
Host smart-2e19597d-dab5-43b1-8702-2a0a46c2dcbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865295105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2865295105
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.4294156684
Short name T58
Test name
Test status
Simulation time 4056876858 ps
CPU time 175.08 seconds
Started Jul 07 04:49:50 PM PDT 24
Finished Jul 07 04:52:46 PM PDT 24
Peak memory 213816 kb
Host smart-35dfddc6-5949-41cf-83bb-9dbc3588da8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294156684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.4294156684
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2177051572
Short name T366
Test name
Test status
Simulation time 3205889939 ps
CPU time 28.12 seconds
Started Jul 07 04:49:51 PM PDT 24
Finished Jul 07 04:50:20 PM PDT 24
Peak memory 216528 kb
Host smart-3f20d349-cb14-4a1a-98c7-b94ce3e631e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177051572 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2177051572
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3356192676
Short name T96
Test name
Test status
Simulation time 667261933 ps
CPU time 13.31 seconds
Started Jul 07 04:49:56 PM PDT 24
Finished Jul 07 04:50:09 PM PDT 24
Peak memory 210568 kb
Host smart-417f92bb-c5f5-4533-b863-b8ca04aa3a19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356192676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3356192676
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3351663889
Short name T436
Test name
Test status
Simulation time 2548384751 ps
CPU time 38.1 seconds
Started Jul 07 04:49:52 PM PDT 24
Finished Jul 07 04:50:31 PM PDT 24
Peak memory 213952 kb
Host smart-4ca29f5b-e57d-473f-a081-3ed6a49b729d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351663889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3351663889
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.807687873
Short name T444
Test name
Test status
Simulation time 9159113957 ps
CPU time 18.95 seconds
Started Jul 07 04:49:51 PM PDT 24
Finished Jul 07 04:50:11 PM PDT 24
Peak memory 211668 kb
Host smart-90a7bdd3-40c9-4e6f-8b40-f16f312bc121
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807687873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.807687873
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2400823933
Short name T386
Test name
Test status
Simulation time 6338070139 ps
CPU time 36.49 seconds
Started Jul 07 04:49:50 PM PDT 24
Finished Jul 07 04:50:27 PM PDT 24
Peak memory 217664 kb
Host smart-44fe6ac4-b9dc-4d3b-8374-c6fbd37e94ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400823933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2400823933
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3272742620
Short name T108
Test name
Test status
Simulation time 6993291377 ps
CPU time 161.45 seconds
Started Jul 07 04:49:49 PM PDT 24
Finished Jul 07 04:52:31 PM PDT 24
Peak memory 214036 kb
Host smart-2b1b037c-13ae-4169-bc3f-2a6ccbb4b5bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272742620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3272742620
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4236174933
Short name T447
Test name
Test status
Simulation time 5545634301 ps
CPU time 28.8 seconds
Started Jul 07 04:49:51 PM PDT 24
Finished Jul 07 04:50:21 PM PDT 24
Peak memory 217488 kb
Host smart-0984d520-a761-4a66-9452-949ab951e8ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236174933 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.4236174933
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4279755912
Short name T438
Test name
Test status
Simulation time 11124184840 ps
CPU time 25.82 seconds
Started Jul 07 04:49:51 PM PDT 24
Finished Jul 07 04:50:17 PM PDT 24
Peak memory 210900 kb
Host smart-e2bc2068-922e-445b-acba-71d0da3205f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279755912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.4279755912
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1424461971
Short name T80
Test name
Test status
Simulation time 25350037071 ps
CPU time 106.67 seconds
Started Jul 07 04:49:52 PM PDT 24
Finished Jul 07 04:51:39 PM PDT 24
Peak memory 213700 kb
Host smart-895cde92-93a7-4067-975e-d93bbc8f3c35
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424461971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1424461971
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.235631825
Short name T94
Test name
Test status
Simulation time 175680707 ps
CPU time 12.42 seconds
Started Jul 07 04:49:53 PM PDT 24
Finished Jul 07 04:50:06 PM PDT 24
Peak memory 212412 kb
Host smart-4c8c1453-8549-4648-8635-45f8626b0127
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235631825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.235631825
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.292264216
Short name T376
Test name
Test status
Simulation time 13453940617 ps
CPU time 32.73 seconds
Started Jul 07 04:49:56 PM PDT 24
Finished Jul 07 04:50:29 PM PDT 24
Peak memory 218896 kb
Host smart-76e9b655-374d-46b5-b1f4-cfe8747f1864
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292264216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.292264216
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3402409291
Short name T443
Test name
Test status
Simulation time 1530015831 ps
CPU time 164.63 seconds
Started Jul 07 04:49:51 PM PDT 24
Finished Jul 07 04:52:36 PM PDT 24
Peak memory 212852 kb
Host smart-da6a273e-3b53-414d-85f0-556e9bf2c65b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402409291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3402409291
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.882229072
Short name T424
Test name
Test status
Simulation time 6836963204 ps
CPU time 28.34 seconds
Started Jul 07 04:50:02 PM PDT 24
Finished Jul 07 04:50:31 PM PDT 24
Peak memory 218460 kb
Host smart-e13c2335-3b8c-476a-881e-626622ec7764
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882229072 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.882229072
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1557107491
Short name T389
Test name
Test status
Simulation time 3419374784 ps
CPU time 28.52 seconds
Started Jul 07 04:49:56 PM PDT 24
Finished Jul 07 04:50:25 PM PDT 24
Peak memory 212056 kb
Host smart-08071fa4-87c4-405f-a7b6-922e72a4bcf8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557107491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1557107491
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2164772094
Short name T368
Test name
Test status
Simulation time 8673701425 ps
CPU time 83.14 seconds
Started Jul 07 04:49:51 PM PDT 24
Finished Jul 07 04:51:15 PM PDT 24
Peak memory 213816 kb
Host smart-14d3803b-6b26-4fb3-96cf-121373f9f06e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164772094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2164772094
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1480525185
Short name T423
Test name
Test status
Simulation time 1648868246 ps
CPU time 11.53 seconds
Started Jul 07 04:49:56 PM PDT 24
Finished Jul 07 04:50:08 PM PDT 24
Peak memory 211168 kb
Host smart-73b03ee7-0c47-4da6-9763-0fcd18a78c03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480525185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1480525185
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3117165925
Short name T388
Test name
Test status
Simulation time 21576106913 ps
CPU time 25.83 seconds
Started Jul 07 04:49:55 PM PDT 24
Finished Jul 07 04:50:22 PM PDT 24
Peak memory 218536 kb
Host smart-de8ca98c-96a3-4871-9664-1fb17da15d62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117165925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3117165925
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1904332463
Short name T370
Test name
Test status
Simulation time 663118570 ps
CPU time 83.6 seconds
Started Jul 07 04:49:55 PM PDT 24
Finished Jul 07 04:51:19 PM PDT 24
Peak memory 213592 kb
Host smart-ac4a7b70-85fa-4227-b69c-b7866b59cf87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904332463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1904332463
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2262009969
Short name T418
Test name
Test status
Simulation time 9359894441 ps
CPU time 29.97 seconds
Started Jul 07 04:49:56 PM PDT 24
Finished Jul 07 04:50:26 PM PDT 24
Peak memory 216704 kb
Host smart-25700630-88da-437e-a336-5dd514fb993e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262009969 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2262009969
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4209459292
Short name T450
Test name
Test status
Simulation time 10152255061 ps
CPU time 23.56 seconds
Started Jul 07 04:49:58 PM PDT 24
Finished Jul 07 04:50:21 PM PDT 24
Peak memory 211624 kb
Host smart-54639963-e6bd-48aa-8d60-2be947d3be46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209459292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.4209459292
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3412676284
Short name T81
Test name
Test status
Simulation time 5688919151 ps
CPU time 91.34 seconds
Started Jul 07 04:50:01 PM PDT 24
Finished Jul 07 04:51:32 PM PDT 24
Peak memory 215772 kb
Host smart-5dc119fe-f285-43b5-80af-18cb4838e302
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412676284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3412676284
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1115678619
Short name T458
Test name
Test status
Simulation time 2391732931 ps
CPU time 12.29 seconds
Started Jul 07 04:49:56 PM PDT 24
Finished Jul 07 04:50:09 PM PDT 24
Peak memory 211312 kb
Host smart-49e69b2b-d724-499c-972a-c0e30da219c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115678619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1115678619
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3182424391
Short name T457
Test name
Test status
Simulation time 647637095 ps
CPU time 17.52 seconds
Started Jul 07 04:49:54 PM PDT 24
Finished Jul 07 04:50:11 PM PDT 24
Peak memory 218544 kb
Host smart-33e190ca-ac59-43be-8528-04f35e677f7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182424391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3182424391
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2187933068
Short name T421
Test name
Test status
Simulation time 2679518998 ps
CPU time 169.19 seconds
Started Jul 07 04:49:55 PM PDT 24
Finished Jul 07 04:52:45 PM PDT 24
Peak memory 213776 kb
Host smart-9f4a1747-f6a7-4051-b96f-1808e66611f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187933068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2187933068
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.4085931785
Short name T230
Test name
Test status
Simulation time 2838762204 ps
CPU time 16.79 seconds
Started Jul 07 04:50:08 PM PDT 24
Finished Jul 07 04:50:25 PM PDT 24
Peak memory 217100 kb
Host smart-3f3f5b36-19b2-47d7-9435-41bc3d3d949a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085931785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.4085931785
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3897583579
Short name T353
Test name
Test status
Simulation time 52867493095 ps
CPU time 173.75 seconds
Started Jul 07 04:50:08 PM PDT 24
Finished Jul 07 04:53:02 PM PDT 24
Peak memory 219416 kb
Host smart-66f2ef8d-3443-4a9e-99d0-d3ad66791064
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897583579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3897583579
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3453950133
Short name T241
Test name
Test status
Simulation time 9158622151 ps
CPU time 35.43 seconds
Started Jul 07 04:50:12 PM PDT 24
Finished Jul 07 04:50:48 PM PDT 24
Peak memory 219312 kb
Host smart-cdc668e4-c200-4830-94e0-ea70939aaca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453950133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3453950133
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3263434327
Short name T171
Test name
Test status
Simulation time 8529464748 ps
CPU time 33.23 seconds
Started Jul 07 04:50:05 PM PDT 24
Finished Jul 07 04:50:39 PM PDT 24
Peak memory 219256 kb
Host smart-a1d033ea-15f2-4787-aafb-092eb567f79a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3263434327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3263434327
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3402197785
Short name T23
Test name
Test status
Simulation time 1322415527 ps
CPU time 232.45 seconds
Started Jul 07 04:50:07 PM PDT 24
Finished Jul 07 04:54:00 PM PDT 24
Peak memory 237904 kb
Host smart-9baf817f-614c-4548-a8c5-89a258d241de
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402197785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3402197785
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.927814312
Short name T258
Test name
Test status
Simulation time 33583263248 ps
CPU time 80.07 seconds
Started Jul 07 04:50:05 PM PDT 24
Finished Jul 07 04:51:26 PM PDT 24
Peak memory 216360 kb
Host smart-896f8163-51d3-4d0c-b958-d1541d8b98cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927814312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.927814312
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3775944265
Short name T278
Test name
Test status
Simulation time 1155592093 ps
CPU time 45.51 seconds
Started Jul 07 04:50:04 PM PDT 24
Finished Jul 07 04:50:50 PM PDT 24
Peak memory 219160 kb
Host smart-3ea214f7-8592-457c-8191-db16d2d2b1cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775944265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3775944265
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.4035019919
Short name T47
Test name
Test status
Simulation time 14418792687 ps
CPU time 562.02 seconds
Started Jul 07 04:50:08 PM PDT 24
Finished Jul 07 04:59:30 PM PDT 24
Peak memory 228476 kb
Host smart-5f81f14d-322d-422f-8310-a7dd03c08048
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035019919 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.4035019919
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1152035029
Short name T224
Test name
Test status
Simulation time 17089237278 ps
CPU time 31.16 seconds
Started Jul 07 04:50:08 PM PDT 24
Finished Jul 07 04:50:40 PM PDT 24
Peak memory 217472 kb
Host smart-2ffe8ac8-aa04-442b-bf6d-f831a659026f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152035029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1152035029
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3476236556
Short name T325
Test name
Test status
Simulation time 5400875995 ps
CPU time 197.52 seconds
Started Jul 07 04:50:08 PM PDT 24
Finished Jul 07 04:53:26 PM PDT 24
Peak memory 237852 kb
Host smart-e07fd411-25c6-4b45-9e3f-f01ac90ccc81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476236556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3476236556
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.4005430478
Short name T333
Test name
Test status
Simulation time 1713053872 ps
CPU time 24.58 seconds
Started Jul 07 04:50:11 PM PDT 24
Finished Jul 07 04:50:35 PM PDT 24
Peak memory 218832 kb
Host smart-40a3c5e7-703b-411d-bc00-4c4e6fe17e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005430478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.4005430478
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.271448452
Short name T210
Test name
Test status
Simulation time 3263327388 ps
CPU time 28.86 seconds
Started Jul 07 04:50:10 PM PDT 24
Finished Jul 07 04:50:39 PM PDT 24
Peak memory 217632 kb
Host smart-23501a48-32f8-46a7-8435-44563c924a50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=271448452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.271448452
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1540869588
Short name T29
Test name
Test status
Simulation time 24047918422 ps
CPU time 41.17 seconds
Started Jul 07 04:50:10 PM PDT 24
Finished Jul 07 04:50:52 PM PDT 24
Peak memory 216792 kb
Host smart-dd991a61-a0a4-49ef-bc6e-0e2d674fb7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540869588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1540869588
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.973256607
Short name T349
Test name
Test status
Simulation time 60802271559 ps
CPU time 59.43 seconds
Started Jul 07 04:50:10 PM PDT 24
Finished Jul 07 04:51:10 PM PDT 24
Peak memory 217080 kb
Host smart-634820da-370d-47e8-b8e5-d95b4922500e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973256607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.973256607
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.904472082
Short name T223
Test name
Test status
Simulation time 1068693955 ps
CPU time 15.49 seconds
Started Jul 07 04:50:24 PM PDT 24
Finished Jul 07 04:50:39 PM PDT 24
Peak memory 216988 kb
Host smart-b5542f76-2aed-4f32-b8f2-e252157065a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904472082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.904472082
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.204229420
Short name T237
Test name
Test status
Simulation time 8851164204 ps
CPU time 219.62 seconds
Started Jul 07 04:50:24 PM PDT 24
Finished Jul 07 04:54:04 PM PDT 24
Peak memory 233988 kb
Host smart-f139ce97-ae74-41b4-8697-8a841bf1721c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204229420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.204229420
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.173990441
Short name T352
Test name
Test status
Simulation time 19138044302 ps
CPU time 35.42 seconds
Started Jul 07 04:50:21 PM PDT 24
Finished Jul 07 04:50:56 PM PDT 24
Peak memory 219208 kb
Host smart-e240cf04-55ce-492f-baeb-6e2d017e0290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173990441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.173990441
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1453046343
Short name T195
Test name
Test status
Simulation time 9355815077 ps
CPU time 25.11 seconds
Started Jul 07 04:50:19 PM PDT 24
Finished Jul 07 04:50:44 PM PDT 24
Peak memory 219336 kb
Host smart-d0084e8e-f4d8-45c4-bec9-085246df790d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1453046343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1453046343
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.260734972
Short name T274
Test name
Test status
Simulation time 6975050741 ps
CPU time 39.95 seconds
Started Jul 07 04:50:23 PM PDT 24
Finished Jul 07 04:51:03 PM PDT 24
Peak memory 217076 kb
Host smart-b02db55a-8c8f-4589-9d90-767d06d70d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260734972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.260734972
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3240245360
Short name T283
Test name
Test status
Simulation time 8296098561 ps
CPU time 52.77 seconds
Started Jul 07 04:50:20 PM PDT 24
Finished Jul 07 04:51:13 PM PDT 24
Peak memory 219272 kb
Host smart-f08e9fd0-5544-4d78-9296-7c647974a57f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240245360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3240245360
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.20448034
Short name T50
Test name
Test status
Simulation time 60698947770 ps
CPU time 1165.98 seconds
Started Jul 07 04:50:23 PM PDT 24
Finished Jul 07 05:09:49 PM PDT 24
Peak memory 233060 kb
Host smart-7972e48f-76ea-4a29-a1a4-313bd1e32b20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20448034 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.20448034
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.787267321
Short name T281
Test name
Test status
Simulation time 9232966596 ps
CPU time 21.88 seconds
Started Jul 07 04:50:24 PM PDT 24
Finished Jul 07 04:50:46 PM PDT 24
Peak memory 217504 kb
Host smart-e84d43a9-1d57-4a8b-b628-837f8bac6405
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787267321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.787267321
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1792675752
Short name T123
Test name
Test status
Simulation time 18666779213 ps
CPU time 232.63 seconds
Started Jul 07 04:50:26 PM PDT 24
Finished Jul 07 04:54:19 PM PDT 24
Peak memory 237844 kb
Host smart-8dc3b15e-fdd2-4f08-9544-8522404ba205
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792675752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1792675752
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2561503028
Short name T139
Test name
Test status
Simulation time 16328036488 ps
CPU time 44.64 seconds
Started Jul 07 04:50:26 PM PDT 24
Finished Jul 07 04:51:11 PM PDT 24
Peak memory 219236 kb
Host smart-56bf63dd-8da9-4118-9095-c3b6bd3fa4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561503028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2561503028
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2753263998
Short name T316
Test name
Test status
Simulation time 16536413203 ps
CPU time 28.62 seconds
Started Jul 07 04:50:21 PM PDT 24
Finished Jul 07 04:50:50 PM PDT 24
Peak memory 219260 kb
Host smart-a42b5dab-34dc-4891-9303-aaef717b65ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2753263998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2753263998
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.994586764
Short name T332
Test name
Test status
Simulation time 7344115371 ps
CPU time 69.89 seconds
Started Jul 07 04:50:20 PM PDT 24
Finished Jul 07 04:51:30 PM PDT 24
Peak memory 217080 kb
Host smart-615ebc9b-6427-4098-8b57-31d872948971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994586764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.994586764
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.537609163
Short name T180
Test name
Test status
Simulation time 9464919417 ps
CPU time 90.25 seconds
Started Jul 07 04:50:22 PM PDT 24
Finished Jul 07 04:51:52 PM PDT 24
Peak memory 219908 kb
Host smart-6361bd5a-a5e5-4f33-ae7c-9e20205b904d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537609163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.537609163
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1434390289
Short name T178
Test name
Test status
Simulation time 1083021842 ps
CPU time 15.13 seconds
Started Jul 07 04:50:30 PM PDT 24
Finished Jul 07 04:50:46 PM PDT 24
Peak memory 216944 kb
Host smart-24d776e4-c4e0-4b15-85e6-1877ad2bad45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434390289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1434390289
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3572477622
Short name T298
Test name
Test status
Simulation time 38898061199 ps
CPU time 410.15 seconds
Started Jul 07 04:50:29 PM PDT 24
Finished Jul 07 04:57:20 PM PDT 24
Peak memory 239404 kb
Host smart-ecd8f674-ead3-4b49-938b-f7dc1571cded
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572477622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3572477622
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.65273755
Short name T9
Test name
Test status
Simulation time 96155257370 ps
CPU time 60.85 seconds
Started Jul 07 04:50:30 PM PDT 24
Finished Jul 07 04:51:31 PM PDT 24
Peak memory 219260 kb
Host smart-da0bde07-162f-48ea-9516-ea089d84f6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65273755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.65273755
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.448079837
Short name T52
Test name
Test status
Simulation time 3938690328 ps
CPU time 32.97 seconds
Started Jul 07 04:50:30 PM PDT 24
Finished Jul 07 04:51:03 PM PDT 24
Peak memory 219256 kb
Host smart-652a061e-8b4d-4f41-9e59-f2341fc77fa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=448079837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.448079837
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.2314821656
Short name T354
Test name
Test status
Simulation time 79739590523 ps
CPU time 57.49 seconds
Started Jul 07 04:50:27 PM PDT 24
Finished Jul 07 04:51:25 PM PDT 24
Peak memory 217096 kb
Host smart-40d47925-297f-4354-813b-575f01a9c670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314821656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.2314821656
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3481471409
Short name T203
Test name
Test status
Simulation time 14294584964 ps
CPU time 149.1 seconds
Started Jul 07 04:50:29 PM PDT 24
Finished Jul 07 04:52:59 PM PDT 24
Peak memory 221144 kb
Host smart-15fecf6e-2e51-4031-b94a-d9fae11118c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481471409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3481471409
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2600530380
Short name T315
Test name
Test status
Simulation time 688751678 ps
CPU time 8.38 seconds
Started Jul 07 04:50:33 PM PDT 24
Finished Jul 07 04:50:42 PM PDT 24
Peak memory 213112 kb
Host smart-2b07cca4-fd27-4e6a-843d-fd0bf65d6796
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600530380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2600530380
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2293282623
Short name T337
Test name
Test status
Simulation time 502996055 ps
CPU time 19.6 seconds
Started Jul 07 04:50:32 PM PDT 24
Finished Jul 07 04:50:52 PM PDT 24
Peak memory 219228 kb
Host smart-6d73932e-a684-444d-9c47-329d084a5fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293282623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2293282623
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2532355014
Short name T235
Test name
Test status
Simulation time 6124489583 ps
CPU time 27.61 seconds
Started Jul 07 04:50:32 PM PDT 24
Finished Jul 07 04:50:59 PM PDT 24
Peak memory 219376 kb
Host smart-28802d7b-20cf-46e3-b611-06edd3b6869e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2532355014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2532355014
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2861372729
Short name T290
Test name
Test status
Simulation time 7259748624 ps
CPU time 62.09 seconds
Started Jul 07 04:50:28 PM PDT 24
Finished Jul 07 04:51:30 PM PDT 24
Peak memory 216492 kb
Host smart-00c772ae-b38f-4f55-8e3c-cddf5ddef98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861372729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2861372729
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1497689742
Short name T28
Test name
Test status
Simulation time 23080154204 ps
CPU time 31.2 seconds
Started Jul 07 04:50:32 PM PDT 24
Finished Jul 07 04:51:04 PM PDT 24
Peak memory 217448 kb
Host smart-5b5e225b-e339-42ee-ac77-a6217451d7dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497689742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1497689742
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1302333731
Short name T205
Test name
Test status
Simulation time 113468222416 ps
CPU time 1155.85 seconds
Started Jul 07 04:50:33 PM PDT 24
Finished Jul 07 05:09:50 PM PDT 24
Peak memory 240180 kb
Host smart-7dd38cf9-8072-4ade-8705-794b66546d0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302333731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1302333731
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3365626019
Short name T212
Test name
Test status
Simulation time 350258085 ps
CPU time 20.1 seconds
Started Jul 07 04:50:33 PM PDT 24
Finished Jul 07 04:50:54 PM PDT 24
Peak memory 219176 kb
Host smart-918c14ed-9bd3-4b4b-bc3e-9ae70c7488cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365626019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3365626019
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2191287683
Short name T236
Test name
Test status
Simulation time 1044088162 ps
CPU time 16.92 seconds
Started Jul 07 04:50:35 PM PDT 24
Finished Jul 07 04:50:53 PM PDT 24
Peak memory 219208 kb
Host smart-b65614cf-f81e-44f4-8618-638dab3e8950
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2191287683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2191287683
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.4161509038
Short name T319
Test name
Test status
Simulation time 714262266 ps
CPU time 20.18 seconds
Started Jul 07 04:50:33 PM PDT 24
Finished Jul 07 04:50:54 PM PDT 24
Peak memory 216020 kb
Host smart-1ddbce88-25f7-46dd-afc5-33ab0e0016c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161509038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.4161509038
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3701981958
Short name T146
Test name
Test status
Simulation time 57965309859 ps
CPU time 112.53 seconds
Started Jul 07 04:50:35 PM PDT 24
Finished Jul 07 04:52:28 PM PDT 24
Peak memory 220744 kb
Host smart-6c6a2f91-7b84-4656-958b-17eb8f44d14c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701981958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3701981958
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1838753329
Short name T326
Test name
Test status
Simulation time 4255562735 ps
CPU time 15.54 seconds
Started Jul 07 04:50:38 PM PDT 24
Finished Jul 07 04:50:54 PM PDT 24
Peak memory 216992 kb
Host smart-62236c68-f051-49ba-89df-0e76c1fd5e7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838753329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1838753329
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.847458248
Short name T191
Test name
Test status
Simulation time 176768857832 ps
CPU time 395.18 seconds
Started Jul 07 04:50:34 PM PDT 24
Finished Jul 07 04:57:10 PM PDT 24
Peak memory 239740 kb
Host smart-b5dba4c8-3841-4097-9768-db61b1349a4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847458248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.847458248
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1769333087
Short name T291
Test name
Test status
Simulation time 11881205421 ps
CPU time 54.41 seconds
Started Jul 07 04:50:37 PM PDT 24
Finished Jul 07 04:51:32 PM PDT 24
Peak memory 219216 kb
Host smart-0d808b41-e56e-4724-be0e-6e341d8e70f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769333087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1769333087
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2528271176
Short name T200
Test name
Test status
Simulation time 225016372 ps
CPU time 10.69 seconds
Started Jul 07 04:50:34 PM PDT 24
Finished Jul 07 04:50:45 PM PDT 24
Peak memory 219092 kb
Host smart-7f46bcf0-7515-4e27-9cd8-84c3d8182afc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2528271176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2528271176
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3921591775
Short name T76
Test name
Test status
Simulation time 15774226576 ps
CPU time 77.55 seconds
Started Jul 07 04:50:34 PM PDT 24
Finished Jul 07 04:51:52 PM PDT 24
Peak memory 216400 kb
Host smart-0c2b1cd5-dea7-4c0e-857d-c2fc4bbfde23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921591775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3921591775
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.622309316
Short name T302
Test name
Test status
Simulation time 78236988274 ps
CPU time 189.48 seconds
Started Jul 07 04:50:37 PM PDT 24
Finished Jul 07 04:53:47 PM PDT 24
Peak memory 221840 kb
Host smart-41a6d5cd-487c-46a3-89e3-6c30bcb13561
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622309316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.622309316
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1121620357
Short name T226
Test name
Test status
Simulation time 10245582995 ps
CPU time 23.82 seconds
Started Jul 07 04:50:42 PM PDT 24
Finished Jul 07 04:51:07 PM PDT 24
Peak memory 217752 kb
Host smart-b7e74253-6a2a-4481-89c9-18358c01911a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121620357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1121620357
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.235391361
Short name T163
Test name
Test status
Simulation time 23876609469 ps
CPU time 376.35 seconds
Started Jul 07 04:50:40 PM PDT 24
Finished Jul 07 04:56:57 PM PDT 24
Peak memory 237660 kb
Host smart-cb6ff9e1-2d81-4487-a915-d0afdcb3d103
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235391361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_c
orrupt_sig_fatal_chk.235391361
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1470743249
Short name T185
Test name
Test status
Simulation time 3417333716 ps
CPU time 41.01 seconds
Started Jul 07 04:50:40 PM PDT 24
Finished Jul 07 04:51:21 PM PDT 24
Peak memory 219260 kb
Host smart-8274e072-9ee5-4ffc-ac2e-f7ea95511972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470743249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1470743249
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1956815559
Short name T116
Test name
Test status
Simulation time 862469241 ps
CPU time 10.23 seconds
Started Jul 07 04:50:42 PM PDT 24
Finished Jul 07 04:50:53 PM PDT 24
Peak memory 219104 kb
Host smart-720520f3-7d7e-42bf-b0e4-1f2bfd8169ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1956815559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1956815559
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1448402938
Short name T75
Test name
Test status
Simulation time 8540990653 ps
CPU time 77.78 seconds
Started Jul 07 04:50:37 PM PDT 24
Finished Jul 07 04:51:55 PM PDT 24
Peak memory 216888 kb
Host smart-0ff971d8-4aa5-4bed-9ee0-7f6c2ba82b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448402938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1448402938
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.701454035
Short name T19
Test name
Test status
Simulation time 9838790979 ps
CPU time 71.72 seconds
Started Jul 07 04:50:37 PM PDT 24
Finished Jul 07 04:51:49 PM PDT 24
Peak memory 217176 kb
Host smart-feea01f2-831b-4032-8453-d49bcfabd59a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701454035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.701454035
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.133128595
Short name T31
Test name
Test status
Simulation time 2485243247 ps
CPU time 22.8 seconds
Started Jul 07 04:50:44 PM PDT 24
Finished Jul 07 04:51:07 PM PDT 24
Peak memory 217168 kb
Host smart-76bc8893-2065-48cd-bbc3-560d752800f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133128595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.133128595
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2892338067
Short name T3
Test name
Test status
Simulation time 27543424969 ps
CPU time 158.39 seconds
Started Jul 07 04:50:43 PM PDT 24
Finished Jul 07 04:53:22 PM PDT 24
Peak memory 219352 kb
Host smart-c17e323d-359f-4d3c-89c9-9cc9fb4a1d51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892338067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2892338067
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.872796437
Short name T249
Test name
Test status
Simulation time 21108130203 ps
CPU time 52.31 seconds
Started Jul 07 04:50:41 PM PDT 24
Finished Jul 07 04:51:34 PM PDT 24
Peak memory 219296 kb
Host smart-5a10c79e-ef96-4910-b598-cca4aa144443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872796437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.872796437
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2299668871
Short name T113
Test name
Test status
Simulation time 3356289700 ps
CPU time 29.14 seconds
Started Jul 07 04:50:43 PM PDT 24
Finished Jul 07 04:51:12 PM PDT 24
Peak memory 219376 kb
Host smart-44469004-afe3-4abe-8e5d-6f3a32664421
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2299668871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2299668871
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.3859157767
Short name T293
Test name
Test status
Simulation time 3592346299 ps
CPU time 39.7 seconds
Started Jul 07 04:50:42 PM PDT 24
Finished Jul 07 04:51:22 PM PDT 24
Peak memory 215996 kb
Host smart-2d8bd5c7-0483-45a8-a0b3-ef095b4e7d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859157767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.3859157767
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.537283553
Short name T276
Test name
Test status
Simulation time 2799192736 ps
CPU time 28.19 seconds
Started Jul 07 04:50:41 PM PDT 24
Finished Jul 07 04:51:09 PM PDT 24
Peak memory 219652 kb
Host smart-1d01122f-86c9-4c1f-94d7-cc31101f371d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537283553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.537283553
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.355190931
Short name T13
Test name
Test status
Simulation time 101974728252 ps
CPU time 1107.29 seconds
Started Jul 07 04:50:42 PM PDT 24
Finished Jul 07 05:09:10 PM PDT 24
Peak memory 243876 kb
Host smart-495af6ed-25a7-4484-a3ee-2231175a70bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355190931 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.355190931
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.115789083
Short name T275
Test name
Test status
Simulation time 21630601372 ps
CPU time 32.11 seconds
Started Jul 07 04:50:41 PM PDT 24
Finished Jul 07 04:51:13 PM PDT 24
Peak memory 217476 kb
Host smart-079fca5e-79ec-4153-a3b3-248592c902e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115789083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.115789083
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.144964444
Short name T128
Test name
Test status
Simulation time 61747935822 ps
CPU time 388.13 seconds
Started Jul 07 04:50:43 PM PDT 24
Finished Jul 07 04:57:12 PM PDT 24
Peak memory 233608 kb
Host smart-20e0cd04-5b20-4961-9336-84d12d856144
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144964444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.144964444
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3230434250
Short name T244
Test name
Test status
Simulation time 4434527397 ps
CPU time 47.97 seconds
Started Jul 07 04:50:42 PM PDT 24
Finished Jul 07 04:51:31 PM PDT 24
Peak memory 219256 kb
Host smart-ad3a75f3-5996-4753-a0ba-e27bfd73d81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230434250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3230434250
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2490119462
Short name T132
Test name
Test status
Simulation time 31701016650 ps
CPU time 33.14 seconds
Started Jul 07 04:50:43 PM PDT 24
Finished Jul 07 04:51:16 PM PDT 24
Peak memory 218020 kb
Host smart-12c97cde-00e0-429e-acf5-44fb4fda2f2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2490119462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2490119462
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.2232698656
Short name T190
Test name
Test status
Simulation time 21421376969 ps
CPU time 54.98 seconds
Started Jul 07 04:50:45 PM PDT 24
Finished Jul 07 04:51:40 PM PDT 24
Peak memory 216884 kb
Host smart-d6e32bac-eba9-49c7-9757-5b44db85f82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232698656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.2232698656
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3713126650
Short name T98
Test name
Test status
Simulation time 18783630565 ps
CPU time 88.03 seconds
Started Jul 07 04:50:45 PM PDT 24
Finished Jul 07 04:52:14 PM PDT 24
Peak memory 219892 kb
Host smart-b98bb44e-340c-4181-8dff-843612e0897f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713126650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3713126650
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3368259943
Short name T300
Test name
Test status
Simulation time 7664667421 ps
CPU time 32.33 seconds
Started Jul 07 04:50:45 PM PDT 24
Finished Jul 07 04:51:18 PM PDT 24
Peak memory 217464 kb
Host smart-35c4813c-bb4e-44b8-a28d-41e95da32fbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368259943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3368259943
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.4130636866
Short name T282
Test name
Test status
Simulation time 2144094114 ps
CPU time 33.81 seconds
Started Jul 07 04:50:46 PM PDT 24
Finished Jul 07 04:51:20 PM PDT 24
Peak memory 219208 kb
Host smart-68a6077e-816f-4950-9058-b549b7a3df04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130636866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.4130636866
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3690023567
Short name T119
Test name
Test status
Simulation time 5180842690 ps
CPU time 25.07 seconds
Started Jul 07 04:50:46 PM PDT 24
Finished Jul 07 04:51:12 PM PDT 24
Peak memory 211776 kb
Host smart-21eaa2fc-68e8-4a98-b181-b97c26050046
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3690023567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3690023567
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3660978742
Short name T99
Test name
Test status
Simulation time 2803792171 ps
CPU time 37.6 seconds
Started Jul 07 04:50:45 PM PDT 24
Finished Jul 07 04:51:23 PM PDT 24
Peak memory 216656 kb
Host smart-8c878c42-b6da-464f-91fa-58dba9ead375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660978742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3660978742
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3032500140
Short name T251
Test name
Test status
Simulation time 766074165 ps
CPU time 24.24 seconds
Started Jul 07 04:50:46 PM PDT 24
Finished Jul 07 04:51:11 PM PDT 24
Peak memory 219168 kb
Host smart-79ede987-c617-444d-8022-78bad571ac6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032500140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3032500140
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2567862809
Short name T65
Test name
Test status
Simulation time 1074960880 ps
CPU time 15.62 seconds
Started Jul 07 04:50:13 PM PDT 24
Finished Jul 07 04:50:29 PM PDT 24
Peak memory 217448 kb
Host smart-96c869de-8caa-4588-a1d8-771fd44c9845
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567862809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2567862809
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1919869788
Short name T328
Test name
Test status
Simulation time 292330777003 ps
CPU time 725.71 seconds
Started Jul 07 04:50:12 PM PDT 24
Finished Jul 07 05:02:19 PM PDT 24
Peak memory 219116 kb
Host smart-fc3dc8e2-1d8e-4b0b-a2d6-e5f2bfeee739
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919869788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1919869788
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2193968111
Short name T97
Test name
Test status
Simulation time 46929040428 ps
CPU time 29.51 seconds
Started Jul 07 04:50:10 PM PDT 24
Finished Jul 07 04:50:40 PM PDT 24
Peak memory 211944 kb
Host smart-92205de5-9990-4108-8a6c-5954991d5752
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2193968111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2193968111
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3296764866
Short name T24
Test name
Test status
Simulation time 14102030558 ps
CPU time 132.76 seconds
Started Jul 07 04:50:10 PM PDT 24
Finished Jul 07 04:52:23 PM PDT 24
Peak memory 236644 kb
Host smart-d7f58807-b477-4788-88da-32f9cba3fcc3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296764866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3296764866
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1252526235
Short name T12
Test name
Test status
Simulation time 5298087564 ps
CPU time 30.25 seconds
Started Jul 07 04:50:12 PM PDT 24
Finished Jul 07 04:50:43 PM PDT 24
Peak memory 216084 kb
Host smart-6189af82-0c41-4ff7-97ac-ada01b65b4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252526235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1252526235
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2270033782
Short name T324
Test name
Test status
Simulation time 4945888421 ps
CPU time 36.32 seconds
Started Jul 07 04:50:07 PM PDT 24
Finished Jul 07 04:50:43 PM PDT 24
Peak memory 217604 kb
Host smart-622d7030-66fc-4ed1-85ea-dc5d5b2b5589
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270033782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2270033782
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.2427595409
Short name T46
Test name
Test status
Simulation time 22003272541 ps
CPU time 881.91 seconds
Started Jul 07 04:50:07 PM PDT 24
Finished Jul 07 05:04:50 PM PDT 24
Peak memory 231816 kb
Host smart-63af0cc7-093d-4ed3-9958-4cd8fadeafdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427595409 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.2427595409
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3421663934
Short name T256
Test name
Test status
Simulation time 2452965450 ps
CPU time 23.55 seconds
Started Jul 07 04:50:45 PM PDT 24
Finished Jul 07 04:51:09 PM PDT 24
Peak memory 217064 kb
Host smart-2a327b6b-40b9-460e-aaf2-826d12a4022a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421663934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3421663934
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.4052539916
Short name T137
Test name
Test status
Simulation time 155925894991 ps
CPU time 892.57 seconds
Started Jul 07 04:50:46 PM PDT 24
Finished Jul 07 05:05:40 PM PDT 24
Peak memory 237936 kb
Host smart-61a5714a-e5a0-47d2-8071-b8fe94bd641b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052539916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.4052539916
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3159974620
Short name T41
Test name
Test status
Simulation time 703897286 ps
CPU time 19.13 seconds
Started Jul 07 04:50:46 PM PDT 24
Finished Jul 07 04:51:05 PM PDT 24
Peak memory 219252 kb
Host smart-8a515cf7-85da-4a80-b540-f77c627489b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159974620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3159974620
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3222553057
Short name T214
Test name
Test status
Simulation time 6637357934 ps
CPU time 28.19 seconds
Started Jul 07 04:50:47 PM PDT 24
Finished Jul 07 04:51:16 PM PDT 24
Peak memory 211820 kb
Host smart-6c45e2d5-c032-4294-8e04-157e2d5a8719
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3222553057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3222553057
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2181513883
Short name T202
Test name
Test status
Simulation time 4949997189 ps
CPU time 51.6 seconds
Started Jul 07 04:50:45 PM PDT 24
Finished Jul 07 04:51:36 PM PDT 24
Peak memory 216484 kb
Host smart-fece3b19-3653-4d1b-bbf8-018aa97c0415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181513883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2181513883
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3532770845
Short name T170
Test name
Test status
Simulation time 800522174 ps
CPU time 51.16 seconds
Started Jul 07 04:50:46 PM PDT 24
Finished Jul 07 04:51:38 PM PDT 24
Peak memory 219248 kb
Host smart-f69cb532-b670-40cc-a831-1828fa1a920e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532770845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3532770845
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.215640691
Short name T347
Test name
Test status
Simulation time 7009695874 ps
CPU time 29.13 seconds
Started Jul 07 04:50:51 PM PDT 24
Finished Jul 07 04:51:21 PM PDT 24
Peak memory 217484 kb
Host smart-a0b08529-9969-41bc-8b05-91028a097508
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215640691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.215640691
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.305228179
Short name T33
Test name
Test status
Simulation time 32080345028 ps
CPU time 405.34 seconds
Started Jul 07 04:50:50 PM PDT 24
Finished Jul 07 04:57:36 PM PDT 24
Peak memory 219500 kb
Host smart-7edfd033-47db-40d0-8809-bdde36266895
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305228179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.305228179
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1198684645
Short name T268
Test name
Test status
Simulation time 30689830358 ps
CPU time 63.7 seconds
Started Jul 07 04:50:52 PM PDT 24
Finished Jul 07 04:51:56 PM PDT 24
Peak memory 219264 kb
Host smart-94d3698a-fe35-4cce-b6ea-ba4181b5cdbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198684645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1198684645
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2396805990
Short name T243
Test name
Test status
Simulation time 507628586 ps
CPU time 14.33 seconds
Started Jul 07 04:50:50 PM PDT 24
Finished Jul 07 04:51:05 PM PDT 24
Peak memory 219220 kb
Host smart-961aaa05-d918-4511-b4cb-b01d407a1e67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2396805990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2396805990
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.1432388533
Short name T239
Test name
Test status
Simulation time 14656175753 ps
CPU time 57.25 seconds
Started Jul 07 04:50:46 PM PDT 24
Finished Jul 07 04:51:44 PM PDT 24
Peak memory 216032 kb
Host smart-4225c029-95d2-4b02-966c-25544a704034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432388533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.1432388533
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1527615715
Short name T188
Test name
Test status
Simulation time 6012120808 ps
CPU time 80.53 seconds
Started Jul 07 04:50:51 PM PDT 24
Finished Jul 07 04:52:12 PM PDT 24
Peak memory 221000 kb
Host smart-183e4077-724f-4035-a5e6-21095a15e94c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527615715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1527615715
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1497915449
Short name T66
Test name
Test status
Simulation time 1916954694 ps
CPU time 20.35 seconds
Started Jul 07 04:50:50 PM PDT 24
Finished Jul 07 04:51:11 PM PDT 24
Peak memory 217200 kb
Host smart-0f6ad657-8c7c-4c42-bcaa-ae0f31b4e18e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497915449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1497915449
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2460315840
Short name T165
Test name
Test status
Simulation time 3117395064 ps
CPU time 201.36 seconds
Started Jul 07 04:50:52 PM PDT 24
Finished Jul 07 04:54:14 PM PDT 24
Peak memory 241596 kb
Host smart-bc7b6019-43b5-416c-8a9d-d8a17f6ab9e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460315840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2460315840
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1298539138
Short name T153
Test name
Test status
Simulation time 4263840896 ps
CPU time 45.05 seconds
Started Jul 07 04:50:52 PM PDT 24
Finished Jul 07 04:51:37 PM PDT 24
Peak memory 219228 kb
Host smart-3178ff9e-6a14-441d-b321-6df0e6b09e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298539138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1298539138
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1738787810
Short name T122
Test name
Test status
Simulation time 927654074 ps
CPU time 16.43 seconds
Started Jul 07 04:50:50 PM PDT 24
Finished Jul 07 04:51:07 PM PDT 24
Peak memory 219256 kb
Host smart-08196927-e542-422d-a578-a14f0392b1a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1738787810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1738787810
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.358851042
Short name T358
Test name
Test status
Simulation time 4529804474 ps
CPU time 47.32 seconds
Started Jul 07 04:50:49 PM PDT 24
Finished Jul 07 04:51:36 PM PDT 24
Peak memory 216628 kb
Host smart-b4201cb8-31d7-4ae6-98b8-c3c1e52d80d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358851042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.358851042
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2667909636
Short name T346
Test name
Test status
Simulation time 3286734861 ps
CPU time 37.05 seconds
Started Jul 07 04:50:51 PM PDT 24
Finished Jul 07 04:51:28 PM PDT 24
Peak memory 214836 kb
Host smart-c85dd7a3-7c94-406b-a0f9-db27487a7841
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667909636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2667909636
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.432574331
Short name T125
Test name
Test status
Simulation time 2849111282 ps
CPU time 26.15 seconds
Started Jul 07 04:50:57 PM PDT 24
Finished Jul 07 04:51:23 PM PDT 24
Peak memory 217216 kb
Host smart-b60aee3f-0277-4cb1-a73d-e1b507f99378
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432574331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.432574331
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.495533973
Short name T247
Test name
Test status
Simulation time 46546966508 ps
CPU time 693.08 seconds
Started Jul 07 04:50:58 PM PDT 24
Finished Jul 07 05:02:31 PM PDT 24
Peak memory 240380 kb
Host smart-07b12ad8-4e6d-425b-9b3e-41e96daf47b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495533973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.495533973
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.770612568
Short name T39
Test name
Test status
Simulation time 346434225 ps
CPU time 19.75 seconds
Started Jul 07 04:51:02 PM PDT 24
Finished Jul 07 04:51:22 PM PDT 24
Peak memory 219252 kb
Host smart-5caf1ceb-09ea-4c02-9bfc-06adfbec00d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770612568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.770612568
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3008328419
Short name T219
Test name
Test status
Simulation time 729828445 ps
CPU time 10.44 seconds
Started Jul 07 04:50:51 PM PDT 24
Finished Jul 07 04:51:02 PM PDT 24
Peak memory 219196 kb
Host smart-14e12a62-72cf-485e-ab74-ab86b6b634e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3008328419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3008328419
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.946497350
Short name T183
Test name
Test status
Simulation time 7006449436 ps
CPU time 33.24 seconds
Started Jul 07 04:50:52 PM PDT 24
Finished Jul 07 04:51:26 PM PDT 24
Peak memory 216604 kb
Host smart-4d683a80-3c83-44ba-ba04-e34436799e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946497350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.946497350
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3529506656
Short name T308
Test name
Test status
Simulation time 27612683552 ps
CPU time 96.53 seconds
Started Jul 07 04:50:50 PM PDT 24
Finished Jul 07 04:52:27 PM PDT 24
Peak memory 222860 kb
Host smart-5d3f6785-1d83-4313-a56c-9114b4155e41
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529506656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3529506656
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.434480889
Short name T303
Test name
Test status
Simulation time 3558676796 ps
CPU time 14.29 seconds
Started Jul 07 04:51:00 PM PDT 24
Finished Jul 07 04:51:15 PM PDT 24
Peak memory 217004 kb
Host smart-089827c5-72a0-441c-a5cc-acfc4ec92232
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434480889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.434480889
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.10676401
Short name T301
Test name
Test status
Simulation time 216447023495 ps
CPU time 654.92 seconds
Started Jul 07 04:50:58 PM PDT 24
Finished Jul 07 05:01:54 PM PDT 24
Peak memory 236528 kb
Host smart-2a48a061-0305-4660-800f-6179cd27712b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10676401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_co
rrupt_sig_fatal_chk.10676401
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.4245307783
Short name T152
Test name
Test status
Simulation time 5221709458 ps
CPU time 34.01 seconds
Started Jul 07 04:50:58 PM PDT 24
Finished Jul 07 04:51:32 PM PDT 24
Peak memory 219296 kb
Host smart-d70a115f-9c7b-4e52-b5b3-265efa7a05d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245307783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.4245307783
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.932957614
Short name T151
Test name
Test status
Simulation time 4984215990 ps
CPU time 24.64 seconds
Started Jul 07 04:50:57 PM PDT 24
Finished Jul 07 04:51:22 PM PDT 24
Peak memory 219276 kb
Host smart-c98caa2b-14b1-4800-821d-16d171dbbc4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=932957614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.932957614
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.2825962188
Short name T142
Test name
Test status
Simulation time 6725549586 ps
CPU time 40.09 seconds
Started Jul 07 04:51:02 PM PDT 24
Finished Jul 07 04:51:42 PM PDT 24
Peak memory 217256 kb
Host smart-24728ad4-9d47-4311-8017-27fba576938a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825962188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.2825962188
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2783731032
Short name T334
Test name
Test status
Simulation time 13889714941 ps
CPU time 114.51 seconds
Started Jul 07 04:50:59 PM PDT 24
Finished Jul 07 04:52:54 PM PDT 24
Peak memory 219652 kb
Host smart-5c7c707d-d1be-474f-bb5e-3b628afc250e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783731032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2783731032
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3319414570
Short name T215
Test name
Test status
Simulation time 1993316040 ps
CPU time 20.75 seconds
Started Jul 07 04:50:59 PM PDT 24
Finished Jul 07 04:51:21 PM PDT 24
Peak memory 217120 kb
Host smart-d4d8dd8e-c458-46c9-b7d1-0ce052e58353
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319414570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3319414570
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3876521428
Short name T144
Test name
Test status
Simulation time 15920575914 ps
CPU time 256.83 seconds
Started Jul 07 04:50:59 PM PDT 24
Finished Jul 07 04:55:17 PM PDT 24
Peak memory 217668 kb
Host smart-9f0cad07-8aec-4cc6-aeb5-8c532d0744e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876521428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3876521428
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2864261836
Short name T213
Test name
Test status
Simulation time 4950306199 ps
CPU time 48.02 seconds
Started Jul 07 04:50:58 PM PDT 24
Finished Jul 07 04:51:47 PM PDT 24
Peak memory 219676 kb
Host smart-a4caa15c-5e5f-4c4a-9714-55c40d47acaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864261836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2864261836
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.44450019
Short name T357
Test name
Test status
Simulation time 3298706086 ps
CPU time 29.23 seconds
Started Jul 07 04:50:57 PM PDT 24
Finished Jul 07 04:51:26 PM PDT 24
Peak memory 211268 kb
Host smart-f2f2a2e1-e8ba-490e-bc7f-8df8c2d86479
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=44450019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.44450019
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.443602116
Short name T271
Test name
Test status
Simulation time 4575271771 ps
CPU time 28.8 seconds
Started Jul 07 04:50:55 PM PDT 24
Finished Jul 07 04:51:24 PM PDT 24
Peak memory 216472 kb
Host smart-20d33638-a79c-4c6b-9f31-5e27f3ae4d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443602116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.443602116
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2489594136
Short name T16
Test name
Test status
Simulation time 3072737558 ps
CPU time 22.64 seconds
Started Jul 07 04:50:57 PM PDT 24
Finished Jul 07 04:51:21 PM PDT 24
Peak memory 217300 kb
Host smart-46bca10d-1842-47c2-a69d-6d118c76dddf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489594136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2489594136
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.536839932
Short name T270
Test name
Test status
Simulation time 41561133883 ps
CPU time 31.9 seconds
Started Jul 07 04:50:58 PM PDT 24
Finished Jul 07 04:51:30 PM PDT 24
Peak memory 217480 kb
Host smart-ab7efd48-db2c-4eb9-bad8-63f77930d01a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536839932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.536839932
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1159213
Short name T159
Test name
Test status
Simulation time 5838220458 ps
CPU time 312.08 seconds
Started Jul 07 04:50:57 PM PDT 24
Finished Jul 07 04:56:10 PM PDT 24
Peak memory 233652 kb
Host smart-f6009e0b-1ed8-4139-8b94-d42fd1b10aa3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_s
ig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_cor
rupt_sig_fatal_chk.1159213
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3761066446
Short name T285
Test name
Test status
Simulation time 2058744184 ps
CPU time 22.39 seconds
Started Jul 07 04:50:58 PM PDT 24
Finished Jul 07 04:51:21 PM PDT 24
Peak memory 218664 kb
Host smart-5118b50c-b48d-45bf-98f2-baae3033bca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761066446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3761066446
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.905773366
Short name T248
Test name
Test status
Simulation time 15059346142 ps
CPU time 31.51 seconds
Started Jul 07 04:50:57 PM PDT 24
Finished Jul 07 04:51:29 PM PDT 24
Peak memory 219232 kb
Host smart-4a560fe7-3852-418c-b532-bdf64de0af72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=905773366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.905773366
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.4000755241
Short name T138
Test name
Test status
Simulation time 1438270500 ps
CPU time 20.39 seconds
Started Jul 07 04:50:58 PM PDT 24
Finished Jul 07 04:51:19 PM PDT 24
Peak memory 216736 kb
Host smart-32ec4042-074b-4cbd-80ff-956bdd9b0dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000755241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.4000755241
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3468301486
Short name T164
Test name
Test status
Simulation time 2350196439 ps
CPU time 8.89 seconds
Started Jul 07 04:50:58 PM PDT 24
Finished Jul 07 04:51:08 PM PDT 24
Peak memory 217012 kb
Host smart-c407a494-cffc-4723-8963-6b5803a1af7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468301486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3468301486
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2399293331
Short name T174
Test name
Test status
Simulation time 102113454450 ps
CPU time 1023.25 seconds
Started Jul 07 04:51:03 PM PDT 24
Finished Jul 07 05:08:07 PM PDT 24
Peak memory 219476 kb
Host smart-54a89d3d-3b8b-49c9-bbae-e7ca79f9c4a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399293331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2399293331
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.188644816
Short name T266
Test name
Test status
Simulation time 5755910617 ps
CPU time 55.05 seconds
Started Jul 07 04:50:59 PM PDT 24
Finished Jul 07 04:51:55 PM PDT 24
Peak memory 219308 kb
Host smart-512d2c6d-2970-433f-a4b1-f2bcb6b7510f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188644816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.188644816
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3358445443
Short name T156
Test name
Test status
Simulation time 6563001669 ps
CPU time 27.83 seconds
Started Jul 07 04:51:01 PM PDT 24
Finished Jul 07 04:51:29 PM PDT 24
Peak memory 211552 kb
Host smart-a0f46d9d-589e-4c03-a370-b59c527a8ef3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3358445443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3358445443
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2749975059
Short name T289
Test name
Test status
Simulation time 5252892421 ps
CPU time 53.61 seconds
Started Jul 07 04:50:58 PM PDT 24
Finished Jul 07 04:51:53 PM PDT 24
Peak memory 216980 kb
Host smart-257b29fd-da39-4bfb-be42-cdc9a3e19510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749975059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2749975059
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2276287813
Short name T148
Test name
Test status
Simulation time 16768564826 ps
CPU time 105.96 seconds
Started Jul 07 04:50:58 PM PDT 24
Finished Jul 07 04:52:45 PM PDT 24
Peak memory 219632 kb
Host smart-4b252690-8622-41d3-9dff-0f5c24bfb7ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276287813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2276287813
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3439117530
Short name T129
Test name
Test status
Simulation time 3919768247 ps
CPU time 29.15 seconds
Started Jul 07 04:50:59 PM PDT 24
Finished Jul 07 04:51:29 PM PDT 24
Peak memory 217228 kb
Host smart-b00711a4-de9c-411d-a843-f9e36c2e64fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439117530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3439117530
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3515649109
Short name T130
Test name
Test status
Simulation time 173248360335 ps
CPU time 552 seconds
Started Jul 07 04:51:00 PM PDT 24
Finished Jul 07 05:00:13 PM PDT 24
Peak memory 240536 kb
Host smart-bce3f47c-75a1-44f9-9d34-d9f81e28a927
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515649109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3515649109
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2576962791
Short name T329
Test name
Test status
Simulation time 1501989700 ps
CPU time 19.01 seconds
Started Jul 07 04:50:59 PM PDT 24
Finished Jul 07 04:51:19 PM PDT 24
Peak memory 219136 kb
Host smart-a7346a36-d0c7-41b7-9935-0eb4c4b808b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576962791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2576962791
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1221228632
Short name T204
Test name
Test status
Simulation time 6068350875 ps
CPU time 27.51 seconds
Started Jul 07 04:51:03 PM PDT 24
Finished Jul 07 04:51:31 PM PDT 24
Peak memory 211592 kb
Host smart-68a00f7c-d239-4110-87e0-ee7e8a805327
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1221228632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1221228632
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1207638108
Short name T297
Test name
Test status
Simulation time 1021790144 ps
CPU time 27.71 seconds
Started Jul 07 04:51:01 PM PDT 24
Finished Jul 07 04:51:29 PM PDT 24
Peak memory 216244 kb
Host smart-7fbf1503-3f1d-45fb-90c8-0d7fd4de510a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207638108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1207638108
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2543318948
Short name T161
Test name
Test status
Simulation time 6480644388 ps
CPU time 20.21 seconds
Started Jul 07 04:51:01 PM PDT 24
Finished Jul 07 04:51:21 PM PDT 24
Peak memory 214724 kb
Host smart-620bbab5-0ffc-4a66-8978-c307d9be8ea5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543318948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2543318948
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2545937441
Short name T288
Test name
Test status
Simulation time 170738413 ps
CPU time 8.37 seconds
Started Jul 07 04:51:03 PM PDT 24
Finished Jul 07 04:51:12 PM PDT 24
Peak memory 218084 kb
Host smart-4332a55a-cde5-4fef-aae5-934b20829061
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545937441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2545937441
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3213631933
Short name T53
Test name
Test status
Simulation time 4629418481 ps
CPU time 49.25 seconds
Started Jul 07 04:51:03 PM PDT 24
Finished Jul 07 04:51:53 PM PDT 24
Peak memory 219260 kb
Host smart-c9d44164-696f-42fb-b0c2-c5fe706f0ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213631933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3213631933
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1125272411
Short name T321
Test name
Test status
Simulation time 1520039998 ps
CPU time 15.82 seconds
Started Jul 07 04:51:05 PM PDT 24
Finished Jul 07 04:51:21 PM PDT 24
Peak memory 219172 kb
Host smart-160ea1b3-91c2-41aa-8621-6fdcde0a24ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1125272411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1125272411
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2311794909
Short name T78
Test name
Test status
Simulation time 17071271815 ps
CPU time 85 seconds
Started Jul 07 04:51:05 PM PDT 24
Finished Jul 07 04:52:31 PM PDT 24
Peak memory 216600 kb
Host smart-6752a8b4-fc72-46a7-83aa-c605dd052160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311794909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2311794909
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3852725906
Short name T222
Test name
Test status
Simulation time 6430946146 ps
CPU time 69.18 seconds
Started Jul 07 04:51:03 PM PDT 24
Finished Jul 07 04:52:13 PM PDT 24
Peak memory 219224 kb
Host smart-748af83e-7a6d-4252-b981-5fa6c56d70b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852725906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3852725906
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2594747021
Short name T343
Test name
Test status
Simulation time 9178263164 ps
CPU time 22.71 seconds
Started Jul 07 04:50:14 PM PDT 24
Finished Jul 07 04:50:37 PM PDT 24
Peak memory 217380 kb
Host smart-48a6b2a0-c612-4127-a83b-937b237a4a9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594747021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2594747021
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.4001704340
Short name T231
Test name
Test status
Simulation time 38244993950 ps
CPU time 458.95 seconds
Started Jul 07 04:50:12 PM PDT 24
Finished Jul 07 04:57:51 PM PDT 24
Peak memory 239968 kb
Host smart-20ebcd22-17e5-494b-9858-22a09f747b84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001704340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.4001704340
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2706879849
Short name T304
Test name
Test status
Simulation time 345890776 ps
CPU time 19.72 seconds
Started Jul 07 04:50:13 PM PDT 24
Finished Jul 07 04:50:33 PM PDT 24
Peak memory 219208 kb
Host smart-31faf95f-3144-43c6-974a-31cde382987b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706879849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2706879849
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1246299288
Short name T335
Test name
Test status
Simulation time 698530352 ps
CPU time 10.35 seconds
Started Jul 07 04:50:10 PM PDT 24
Finished Jul 07 04:50:20 PM PDT 24
Peak memory 219204 kb
Host smart-972c21b3-4f8f-45d0-a234-4b9f7bac6b6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1246299288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1246299288
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3837818473
Short name T25
Test name
Test status
Simulation time 1782029505 ps
CPU time 120.13 seconds
Started Jul 07 04:50:14 PM PDT 24
Finished Jul 07 04:52:15 PM PDT 24
Peak memory 237384 kb
Host smart-c900a5d4-3d65-4155-a563-571eaf3878f6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837818473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3837818473
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3471804927
Short name T339
Test name
Test status
Simulation time 1233608541 ps
CPU time 19.31 seconds
Started Jul 07 04:50:09 PM PDT 24
Finished Jul 07 04:50:28 PM PDT 24
Peak memory 217020 kb
Host smart-483e07cf-4887-4370-9ccc-0923b13352e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471804927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3471804927
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2582615162
Short name T280
Test name
Test status
Simulation time 713719863 ps
CPU time 43.94 seconds
Started Jul 07 04:50:08 PM PDT 24
Finished Jul 07 04:50:53 PM PDT 24
Peak memory 219256 kb
Host smart-a29fe0ad-ab3a-4d92-b36e-46b7d2f2f246
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582615162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2582615162
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.191790111
Short name T44
Test name
Test status
Simulation time 53618987404 ps
CPU time 4182.33 seconds
Started Jul 07 04:50:12 PM PDT 24
Finished Jul 07 05:59:55 PM PDT 24
Peak memory 232364 kb
Host smart-ebdb1bd6-f32c-433c-99a8-b3b24f0bb173
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191790111 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.191790111
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1153446965
Short name T228
Test name
Test status
Simulation time 6658029903 ps
CPU time 23.06 seconds
Started Jul 07 04:51:03 PM PDT 24
Finished Jul 07 04:51:26 PM PDT 24
Peak memory 217440 kb
Host smart-249e2e4f-be88-4d19-a07a-13c9d93f6855
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153446965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1153446965
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1188321482
Short name T253
Test name
Test status
Simulation time 7890539983 ps
CPU time 330.29 seconds
Started Jul 07 04:51:04 PM PDT 24
Finished Jul 07 04:56:35 PM PDT 24
Peak memory 219516 kb
Host smart-bc49e384-610b-4a26-a623-d85f6ddd43bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188321482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1188321482
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.143993973
Short name T177
Test name
Test status
Simulation time 7199003646 ps
CPU time 31.24 seconds
Started Jul 07 04:51:03 PM PDT 24
Finished Jul 07 04:51:35 PM PDT 24
Peak memory 219320 kb
Host smart-040e69e7-87d1-4e0c-8044-607b9f497b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143993973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.143993973
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2661304892
Short name T322
Test name
Test status
Simulation time 694220825 ps
CPU time 10.75 seconds
Started Jul 07 04:51:03 PM PDT 24
Finished Jul 07 04:51:14 PM PDT 24
Peak memory 219216 kb
Host smart-24ea106a-422b-4cee-8043-086409dc72d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2661304892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2661304892
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.48128207
Short name T211
Test name
Test status
Simulation time 3943480040 ps
CPU time 43.61 seconds
Started Jul 07 04:51:04 PM PDT 24
Finished Jul 07 04:51:48 PM PDT 24
Peak memory 216836 kb
Host smart-97b4fcd2-cbd9-49a5-9e8f-a73f9ac711ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48128207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.48128207
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2100562268
Short name T114
Test name
Test status
Simulation time 2496988840 ps
CPU time 24.92 seconds
Started Jul 07 04:51:04 PM PDT 24
Finished Jul 07 04:51:30 PM PDT 24
Peak memory 214604 kb
Host smart-bcc85934-dd35-4a84-8802-3dc5f3fe691b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100562268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2100562268
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.827530516
Short name T279
Test name
Test status
Simulation time 12116277552 ps
CPU time 25.96 seconds
Started Jul 07 04:51:04 PM PDT 24
Finished Jul 07 04:51:30 PM PDT 24
Peak memory 213256 kb
Host smart-c6421505-230a-47be-aef6-0dbdd71091a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827530516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.827530516
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1695701630
Short name T199
Test name
Test status
Simulation time 20096893562 ps
CPU time 288.93 seconds
Started Jul 07 04:51:06 PM PDT 24
Finished Jul 07 04:55:56 PM PDT 24
Peak memory 227644 kb
Host smart-3c50e7f6-2b2c-4f50-9d8b-024c15f06d59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695701630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1695701630
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.160745370
Short name T55
Test name
Test status
Simulation time 1309435446 ps
CPU time 28.27 seconds
Started Jul 07 04:51:04 PM PDT 24
Finished Jul 07 04:51:32 PM PDT 24
Peak memory 218784 kb
Host smart-d411d0e4-0062-4553-b97b-040a742cfc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160745370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.160745370
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.4169028067
Short name T254
Test name
Test status
Simulation time 8939980669 ps
CPU time 22.42 seconds
Started Jul 07 04:51:03 PM PDT 24
Finished Jul 07 04:51:26 PM PDT 24
Peak memory 211816 kb
Host smart-4de90a21-ade7-4d87-aef0-1ab481a50d26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4169028067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.4169028067
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1524002403
Short name T277
Test name
Test status
Simulation time 716894096 ps
CPU time 20.33 seconds
Started Jul 07 04:51:06 PM PDT 24
Finished Jul 07 04:51:26 PM PDT 24
Peak memory 216268 kb
Host smart-1636536f-3c53-44a3-901e-6de532d11d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524002403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1524002403
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2828115092
Short name T17
Test name
Test status
Simulation time 49280174787 ps
CPU time 116.87 seconds
Started Jul 07 04:51:05 PM PDT 24
Finished Jul 07 04:53:03 PM PDT 24
Peak memory 221484 kb
Host smart-0ae8b00f-fec8-4405-b76d-10fb63b04785
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828115092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2828115092
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2875849826
Short name T257
Test name
Test status
Simulation time 687755124 ps
CPU time 8.34 seconds
Started Jul 07 04:51:08 PM PDT 24
Finished Jul 07 04:51:16 PM PDT 24
Peak memory 217060 kb
Host smart-af3d788d-53c7-48ac-9618-d58a154b0c6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875849826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2875849826
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.517729484
Short name T36
Test name
Test status
Simulation time 187752140708 ps
CPU time 668.68 seconds
Started Jul 07 04:51:06 PM PDT 24
Finished Jul 07 05:02:15 PM PDT 24
Peak memory 236328 kb
Host smart-0a56b3f0-66f8-4d3e-b421-c801af3a17db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517729484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.517729484
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.4108574
Short name T317
Test name
Test status
Simulation time 8438185769 ps
CPU time 67.56 seconds
Started Jul 07 04:51:08 PM PDT 24
Finished Jul 07 04:52:16 PM PDT 24
Peak memory 219316 kb
Host smart-ae5b9c8f-7003-4af9-abc2-120386084916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.4108574
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3343451269
Short name T147
Test name
Test status
Simulation time 183846473 ps
CPU time 10.34 seconds
Started Jul 07 04:51:09 PM PDT 24
Finished Jul 07 04:51:19 PM PDT 24
Peak memory 219244 kb
Host smart-82b04b25-d16c-4aa0-9a1a-d9b30ce0dde8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3343451269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3343451269
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1093816483
Short name T115
Test name
Test status
Simulation time 57853397443 ps
CPU time 42.02 seconds
Started Jul 07 04:51:04 PM PDT 24
Finished Jul 07 04:51:46 PM PDT 24
Peak memory 216492 kb
Host smart-00e85ea0-2496-4218-946a-df655b4b0c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093816483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1093816483
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3166449857
Short name T150
Test name
Test status
Simulation time 3604109558 ps
CPU time 15.62 seconds
Started Jul 07 04:51:05 PM PDT 24
Finished Jul 07 04:51:21 PM PDT 24
Peak memory 219172 kb
Host smart-bb56a4bb-f65e-45a8-a296-d7fd244298c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166449857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3166449857
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2800100471
Short name T342
Test name
Test status
Simulation time 3163398812 ps
CPU time 18.78 seconds
Started Jul 07 04:51:08 PM PDT 24
Finished Jul 07 04:51:27 PM PDT 24
Peak memory 217064 kb
Host smart-c596cc3e-1ded-4025-bef6-dce4c509f2d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800100471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2800100471
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.4021842459
Short name T207
Test name
Test status
Simulation time 7378987469 ps
CPU time 123.37 seconds
Started Jul 07 04:51:08 PM PDT 24
Finished Jul 07 04:53:12 PM PDT 24
Peak memory 227208 kb
Host smart-6811ff77-d1fd-45d8-af1e-7c5fc73d9b03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021842459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.4021842459
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1832115013
Short name T299
Test name
Test status
Simulation time 5482435476 ps
CPU time 29.68 seconds
Started Jul 07 04:51:07 PM PDT 24
Finished Jul 07 04:51:37 PM PDT 24
Peak memory 218864 kb
Host smart-f24b1b22-b6e6-47c3-a647-04d265a1329b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832115013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1832115013
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2183919073
Short name T187
Test name
Test status
Simulation time 2880860038 ps
CPU time 26.07 seconds
Started Jul 07 04:51:08 PM PDT 24
Finished Jul 07 04:51:35 PM PDT 24
Peak memory 211344 kb
Host smart-b72af929-c402-4e69-9dde-610d59ea4f0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2183919073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2183919073
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1382349960
Short name T341
Test name
Test status
Simulation time 5811062099 ps
CPU time 27.2 seconds
Started Jul 07 04:51:08 PM PDT 24
Finished Jul 07 04:51:36 PM PDT 24
Peak memory 217020 kb
Host smart-65945ff0-360f-49d1-964a-1ee0c7b87da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382349960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1382349960
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.876508127
Short name T345
Test name
Test status
Simulation time 8998879602 ps
CPU time 135.89 seconds
Started Jul 07 04:51:08 PM PDT 24
Finished Jul 07 04:53:24 PM PDT 24
Peak memory 220076 kb
Host smart-1d760527-8eaa-43ee-b5af-94d63040d24a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876508127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.876508127
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1310987405
Short name T133
Test name
Test status
Simulation time 4250694858 ps
CPU time 21.72 seconds
Started Jul 07 04:51:12 PM PDT 24
Finished Jul 07 04:51:34 PM PDT 24
Peak memory 213172 kb
Host smart-c08d0967-59e4-446d-bb8c-49c5f529d79b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310987405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1310987405
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2833741189
Short name T292
Test name
Test status
Simulation time 230324024759 ps
CPU time 534.54 seconds
Started Jul 07 04:51:08 PM PDT 24
Finished Jul 07 05:00:03 PM PDT 24
Peak memory 235220 kb
Host smart-f3404034-8d33-4444-a4b0-b8b95310428d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833741189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2833741189
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2763629609
Short name T140
Test name
Test status
Simulation time 31556510919 ps
CPU time 64.61 seconds
Started Jul 07 04:51:08 PM PDT 24
Finished Jul 07 04:52:13 PM PDT 24
Peak memory 219132 kb
Host smart-74a20ea5-b1a1-484c-8798-7d7ebdd35181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763629609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2763629609
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.434983801
Short name T192
Test name
Test status
Simulation time 3263472919 ps
CPU time 28.69 seconds
Started Jul 07 04:51:05 PM PDT 24
Finished Jul 07 04:51:34 PM PDT 24
Peak memory 219336 kb
Host smart-16451f68-3839-4e48-afa0-2fdc6712c5be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=434983801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.434983801
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.3176098081
Short name T229
Test name
Test status
Simulation time 15723691972 ps
CPU time 61.73 seconds
Started Jul 07 04:51:06 PM PDT 24
Finished Jul 07 04:52:08 PM PDT 24
Peak memory 215644 kb
Host smart-3b20b7b3-06bc-48fa-98d3-3051b188b95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176098081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.3176098081
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2804107058
Short name T134
Test name
Test status
Simulation time 49381874292 ps
CPU time 103.08 seconds
Started Jul 07 04:51:15 PM PDT 24
Finished Jul 07 04:52:58 PM PDT 24
Peak memory 219284 kb
Host smart-775eb693-928d-45e2-becf-db3c9b231fdb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804107058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2804107058
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.219275646
Short name T45
Test name
Test status
Simulation time 146701590198 ps
CPU time 4221.39 seconds
Started Jul 07 04:51:12 PM PDT 24
Finished Jul 07 06:01:34 PM PDT 24
Peak memory 252108 kb
Host smart-333c2f47-31ed-4e28-9596-eed0aa8a2038
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219275646 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.219275646
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1683790242
Short name T4
Test name
Test status
Simulation time 902999417 ps
CPU time 14.46 seconds
Started Jul 07 04:51:12 PM PDT 24
Finished Jul 07 04:51:27 PM PDT 24
Peak memory 216996 kb
Host smart-20a80d40-e276-4227-be9b-c98f26bdfe81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683790242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1683790242
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.82322455
Short name T21
Test name
Test status
Simulation time 172622332517 ps
CPU time 479.56 seconds
Started Jul 07 04:51:11 PM PDT 24
Finished Jul 07 04:59:11 PM PDT 24
Peak memory 233524 kb
Host smart-83ecc8f2-f750-4d38-a9e9-2eff01b6d9e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82322455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_co
rrupt_sig_fatal_chk.82322455
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2930184681
Short name T287
Test name
Test status
Simulation time 11343679431 ps
CPU time 47.68 seconds
Started Jul 07 04:51:12 PM PDT 24
Finished Jul 07 04:52:00 PM PDT 24
Peak memory 219372 kb
Host smart-448bf3f4-259a-423a-9a36-1fdf410719d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930184681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2930184681
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1052416946
Short name T149
Test name
Test status
Simulation time 11057859222 ps
CPU time 26.49 seconds
Started Jul 07 04:51:12 PM PDT 24
Finished Jul 07 04:51:39 PM PDT 24
Peak memory 211908 kb
Host smart-2b5f5857-a884-4b34-9f38-1ff5e19232d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1052416946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1052416946
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.2413942126
Short name T336
Test name
Test status
Simulation time 2342802487 ps
CPU time 35.42 seconds
Started Jul 07 04:51:12 PM PDT 24
Finished Jul 07 04:51:48 PM PDT 24
Peak memory 216228 kb
Host smart-4a3ce24b-c162-4c7b-a150-5a09dc89e9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413942126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.2413942126
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.4049608139
Short name T54
Test name
Test status
Simulation time 5950151961 ps
CPU time 79.49 seconds
Started Jul 07 04:51:13 PM PDT 24
Finished Jul 07 04:52:33 PM PDT 24
Peak memory 219248 kb
Host smart-dcc6cbbc-627b-49a5-941f-29e9e7afecb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049608139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.4049608139
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2484187821
Short name T216
Test name
Test status
Simulation time 14347180468 ps
CPU time 29.89 seconds
Started Jul 07 04:51:12 PM PDT 24
Finished Jul 07 04:51:42 PM PDT 24
Peak memory 217356 kb
Host smart-9d96aa70-f5e8-4169-810b-a790aac01dd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484187821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2484187821
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3536973815
Short name T42
Test name
Test status
Simulation time 111883064132 ps
CPU time 593.72 seconds
Started Jul 07 04:51:11 PM PDT 24
Finished Jul 07 05:01:05 PM PDT 24
Peak memory 225632 kb
Host smart-f1415f16-8903-4ae5-94dd-94f5ab7c5310
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536973815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3536973815
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.177167352
Short name T136
Test name
Test status
Simulation time 113032502976 ps
CPU time 65.05 seconds
Started Jul 07 04:51:13 PM PDT 24
Finished Jul 07 04:52:18 PM PDT 24
Peak memory 219332 kb
Host smart-c1e37fdb-1c01-4c12-b452-84947500b6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177167352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.177167352
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2497328374
Short name T30
Test name
Test status
Simulation time 1549769585 ps
CPU time 19.75 seconds
Started Jul 07 04:51:13 PM PDT 24
Finished Jul 07 04:51:33 PM PDT 24
Peak memory 211192 kb
Host smart-9c38a608-a08e-4197-81e9-a6f6cbf013d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2497328374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2497328374
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.477047625
Short name T209
Test name
Test status
Simulation time 12440827656 ps
CPU time 44.73 seconds
Started Jul 07 04:51:11 PM PDT 24
Finished Jul 07 04:51:56 PM PDT 24
Peak memory 217148 kb
Host smart-3a9ef58a-6736-4d02-a1d1-9f5a501f863b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477047625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.477047625
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.146479155
Short name T124
Test name
Test status
Simulation time 5033627730 ps
CPU time 52.22 seconds
Started Jul 07 04:51:15 PM PDT 24
Finished Jul 07 04:52:08 PM PDT 24
Peak memory 216256 kb
Host smart-f4c1b3bd-9e9f-4f27-8dcc-917a76e70c07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146479155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.146479155
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1098262905
Short name T264
Test name
Test status
Simulation time 11170586596 ps
CPU time 23.96 seconds
Started Jul 07 04:51:15 PM PDT 24
Finished Jul 07 04:51:39 PM PDT 24
Peak memory 217452 kb
Host smart-f601e2b2-cc65-4ea5-96a2-c33f3ae8c51d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098262905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1098262905
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3504555867
Short name T34
Test name
Test status
Simulation time 11626904427 ps
CPU time 244.47 seconds
Started Jul 07 04:51:17 PM PDT 24
Finished Jul 07 04:55:22 PM PDT 24
Peak memory 237812 kb
Host smart-8ba313a8-4c47-40e5-9141-0fc549a9595f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504555867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3504555867
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.701826230
Short name T118
Test name
Test status
Simulation time 1481826689 ps
CPU time 29.75 seconds
Started Jul 07 04:51:15 PM PDT 24
Finished Jul 07 04:51:45 PM PDT 24
Peak memory 219180 kb
Host smart-b6cddd9c-e4aa-41e5-93b5-690c6190f686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701826230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.701826230
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3784681142
Short name T141
Test name
Test status
Simulation time 29065439740 ps
CPU time 24.69 seconds
Started Jul 07 04:51:14 PM PDT 24
Finished Jul 07 04:51:39 PM PDT 24
Peak memory 219268 kb
Host smart-2bd6c235-30ad-4b79-85ce-134e85869d21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3784681142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3784681142
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.4178650519
Short name T351
Test name
Test status
Simulation time 3359007915 ps
CPU time 20.42 seconds
Started Jul 07 04:51:11 PM PDT 24
Finished Jul 07 04:51:32 PM PDT 24
Peak memory 217436 kb
Host smart-137caabf-5ef7-48db-a131-51de863cf242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178650519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.4178650519
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1693971567
Short name T286
Test name
Test status
Simulation time 12232175360 ps
CPU time 61.04 seconds
Started Jul 07 04:51:17 PM PDT 24
Finished Jul 07 04:52:19 PM PDT 24
Peak memory 217040 kb
Host smart-2fed9d52-7e83-4737-b56a-c3ac57e89be2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693971567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1693971567
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1934368690
Short name T135
Test name
Test status
Simulation time 13605969896 ps
CPU time 20.64 seconds
Started Jul 07 04:51:16 PM PDT 24
Finished Jul 07 04:51:37 PM PDT 24
Peak memory 217440 kb
Host smart-4e01f7b6-be40-4905-b17a-ff80d5e79dda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934368690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1934368690
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2479311110
Short name T162
Test name
Test status
Simulation time 22524192018 ps
CPU time 404.02 seconds
Started Jul 07 04:51:15 PM PDT 24
Finished Jul 07 04:58:00 PM PDT 24
Peak memory 233884 kb
Host smart-30f399d1-86bd-45a5-9508-c6a51c9848d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479311110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2479311110
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3124422592
Short name T232
Test name
Test status
Simulation time 1320521567 ps
CPU time 19.87 seconds
Started Jul 07 04:51:14 PM PDT 24
Finished Jul 07 04:51:34 PM PDT 24
Peak memory 219224 kb
Host smart-b35a01ad-a31d-447b-a7e8-90eb67818ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124422592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3124422592
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1889361293
Short name T259
Test name
Test status
Simulation time 4197255968 ps
CPU time 30.53 seconds
Started Jul 07 04:51:16 PM PDT 24
Finished Jul 07 04:51:47 PM PDT 24
Peak memory 211228 kb
Host smart-8029b7b7-b13f-4b47-9f13-d8e91cf047ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1889361293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1889361293
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.4049942645
Short name T20
Test name
Test status
Simulation time 1380212922 ps
CPU time 20.36 seconds
Started Jul 07 04:51:17 PM PDT 24
Finished Jul 07 04:51:37 PM PDT 24
Peak memory 216188 kb
Host smart-8d0a3421-5f8a-4d7e-a494-cdd1e79cdc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049942645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.4049942645
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.370548858
Short name T296
Test name
Test status
Simulation time 756268173 ps
CPU time 44.73 seconds
Started Jul 07 04:51:18 PM PDT 24
Finished Jul 07 04:52:03 PM PDT 24
Peak memory 219232 kb
Host smart-18713dc7-f622-45ab-8e78-1f0e55337a90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370548858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.370548858
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.2955418370
Short name T48
Test name
Test status
Simulation time 91727222516 ps
CPU time 917.11 seconds
Started Jul 07 04:51:18 PM PDT 24
Finished Jul 07 05:06:35 PM PDT 24
Peak memory 233624 kb
Host smart-56f19ed6-de0d-4e47-ab95-875fa09b880f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955418370 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.2955418370
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3947421601
Short name T6
Test name
Test status
Simulation time 167553375 ps
CPU time 8.5 seconds
Started Jul 07 04:51:21 PM PDT 24
Finished Jul 07 04:51:30 PM PDT 24
Peak memory 217016 kb
Host smart-bf67ac24-7267-47bf-a0ab-1b2d8c73d764
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947421601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3947421601
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.700078477
Short name T265
Test name
Test status
Simulation time 115945753460 ps
CPU time 965.12 seconds
Started Jul 07 04:51:26 PM PDT 24
Finished Jul 07 05:07:32 PM PDT 24
Peak memory 225872 kb
Host smart-388e253b-ca43-45dc-94e7-9588fc37deae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700078477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.700078477
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.982901511
Short name T120
Test name
Test status
Simulation time 1034926708 ps
CPU time 26.57 seconds
Started Jul 07 04:51:20 PM PDT 24
Finished Jul 07 04:51:47 PM PDT 24
Peak memory 219316 kb
Host smart-fdd43bb7-3977-44df-91bc-7645acef01dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982901511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.982901511
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3720552949
Short name T242
Test name
Test status
Simulation time 181936737 ps
CPU time 10.53 seconds
Started Jul 07 04:51:26 PM PDT 24
Finished Jul 07 04:51:37 PM PDT 24
Peak memory 219208 kb
Host smart-9b8b5814-2520-4d44-90d4-a9117437a9ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3720552949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3720552949
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1501647560
Short name T309
Test name
Test status
Simulation time 8334274293 ps
CPU time 79.72 seconds
Started Jul 07 04:51:22 PM PDT 24
Finished Jul 07 04:52:42 PM PDT 24
Peak memory 215584 kb
Host smart-99626ff7-6a33-4bdd-b658-69269e1a8af9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501647560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1501647560
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2104838055
Short name T181
Test name
Test status
Simulation time 612915131 ps
CPU time 8.4 seconds
Started Jul 07 04:50:11 PM PDT 24
Finished Jul 07 04:50:20 PM PDT 24
Peak memory 213184 kb
Host smart-a50e65da-a601-40dd-bae9-26b101a95c60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104838055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2104838055
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.4176446955
Short name T323
Test name
Test status
Simulation time 128806595621 ps
CPU time 390.87 seconds
Started Jul 07 04:50:15 PM PDT 24
Finished Jul 07 04:56:46 PM PDT 24
Peak memory 227392 kb
Host smart-835ad8ee-f68f-4e2a-90a0-809fc3e83c60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176446955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.4176446955
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2386403571
Short name T313
Test name
Test status
Simulation time 1739145232 ps
CPU time 19.38 seconds
Started Jul 07 04:50:23 PM PDT 24
Finished Jul 07 04:50:42 PM PDT 24
Peak memory 219256 kb
Host smart-42c54758-76ca-4fcc-94b1-36bd119449bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386403571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2386403571
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.876451300
Short name T272
Test name
Test status
Simulation time 18264430948 ps
CPU time 28.92 seconds
Started Jul 07 04:50:13 PM PDT 24
Finished Jul 07 04:50:42 PM PDT 24
Peak memory 211944 kb
Host smart-1940e564-e24f-40f5-b1ce-72da4aeeb667
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=876451300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.876451300
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3171517402
Short name T26
Test name
Test status
Simulation time 4749022853 ps
CPU time 252.4 seconds
Started Jul 07 04:50:12 PM PDT 24
Finished Jul 07 04:54:25 PM PDT 24
Peak memory 236292 kb
Host smart-4c0856a9-1e0a-4264-8256-387d27e8c8f1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171517402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3171517402
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.124421753
Short name T56
Test name
Test status
Simulation time 8024745281 ps
CPU time 65.6 seconds
Started Jul 07 04:50:13 PM PDT 24
Finished Jul 07 04:51:19 PM PDT 24
Peak memory 216408 kb
Host smart-9c13311b-2286-464c-9f61-c8584584a168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124421753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.124421753
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2769124644
Short name T186
Test name
Test status
Simulation time 978971729 ps
CPU time 23.2 seconds
Started Jul 07 04:50:11 PM PDT 24
Finished Jul 07 04:50:35 PM PDT 24
Peak memory 219248 kb
Host smart-e5026554-20f4-4ab0-ace6-2303b61d7132
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769124644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2769124644
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1921038084
Short name T121
Test name
Test status
Simulation time 3683219777 ps
CPU time 13.38 seconds
Started Jul 07 04:51:25 PM PDT 24
Finished Jul 07 04:51:39 PM PDT 24
Peak memory 217196 kb
Host smart-b7e5e4d3-f97f-4788-bbf6-9b5a472f7546
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921038084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1921038084
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1020514795
Short name T318
Test name
Test status
Simulation time 68776952601 ps
CPU time 678.06 seconds
Started Jul 07 04:51:28 PM PDT 24
Finished Jul 07 05:02:46 PM PDT 24
Peak memory 235920 kb
Host smart-a57cea8b-11a5-4a69-9a9d-5dce5a95effc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020514795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1020514795
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.255493334
Short name T273
Test name
Test status
Simulation time 2340802406 ps
CPU time 34.87 seconds
Started Jul 07 04:51:26 PM PDT 24
Finished Jul 07 04:52:01 PM PDT 24
Peak memory 219400 kb
Host smart-01c802fa-7c30-476f-a26b-7c7fd7856aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255493334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.255493334
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3759727896
Short name T295
Test name
Test status
Simulation time 3700525404 ps
CPU time 17.1 seconds
Started Jul 07 04:51:27 PM PDT 24
Finished Jul 07 04:51:44 PM PDT 24
Peak memory 219264 kb
Host smart-027dcc14-de73-465c-822c-95081495c8bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3759727896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3759727896
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.4097203631
Short name T255
Test name
Test status
Simulation time 21695953809 ps
CPU time 48.07 seconds
Started Jul 07 04:51:20 PM PDT 24
Finished Jul 07 04:52:08 PM PDT 24
Peak memory 216752 kb
Host smart-76c785b8-5678-4876-a645-1f4112870a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097203631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.4097203631
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1041580616
Short name T233
Test name
Test status
Simulation time 35024527651 ps
CPU time 261.81 seconds
Started Jul 07 04:51:26 PM PDT 24
Finished Jul 07 04:55:48 PM PDT 24
Peak memory 220180 kb
Host smart-20123e7a-f818-4463-aa8a-f580bf35b7e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041580616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1041580616
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2395131542
Short name T221
Test name
Test status
Simulation time 12515673531 ps
CPU time 28.66 seconds
Started Jul 07 04:51:31 PM PDT 24
Finished Jul 07 04:52:00 PM PDT 24
Peak memory 217536 kb
Host smart-5cbcb207-0b97-4f82-a3ff-3a9a5fbcb53c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395131542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2395131542
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2448217433
Short name T250
Test name
Test status
Simulation time 30608432028 ps
CPU time 148.84 seconds
Started Jul 07 04:51:25 PM PDT 24
Finished Jul 07 04:53:55 PM PDT 24
Peak memory 229112 kb
Host smart-5e7fa7ca-f765-4eba-99d8-9b23f5e13daa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448217433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2448217433
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1825160857
Short name T175
Test name
Test status
Simulation time 4260608416 ps
CPU time 46.35 seconds
Started Jul 07 04:51:26 PM PDT 24
Finished Jul 07 04:52:12 PM PDT 24
Peak memory 219276 kb
Host smart-e3f577e3-7aa3-430b-a209-b7af33376e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825160857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1825160857
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3817360533
Short name T311
Test name
Test status
Simulation time 1657361315 ps
CPU time 19.68 seconds
Started Jul 07 04:51:29 PM PDT 24
Finished Jul 07 04:51:49 PM PDT 24
Peak memory 219180 kb
Host smart-7e7eec79-8b2b-4d2c-bf64-652eea86c961
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3817360533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3817360533
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.2741580785
Short name T261
Test name
Test status
Simulation time 688746091 ps
CPU time 20.6 seconds
Started Jul 07 04:51:25 PM PDT 24
Finished Jul 07 04:51:45 PM PDT 24
Peak memory 216220 kb
Host smart-e8318b29-b839-4e82-b2df-da16e6db546d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741580785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.2741580785
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3722314326
Short name T169
Test name
Test status
Simulation time 5421327392 ps
CPU time 86.05 seconds
Started Jul 07 04:51:28 PM PDT 24
Finished Jul 07 04:52:55 PM PDT 24
Peak memory 227696 kb
Host smart-567543e3-b520-4254-9a78-12bac0e8c373
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722314326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3722314326
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.4094930948
Short name T338
Test name
Test status
Simulation time 660933380 ps
CPU time 8.28 seconds
Started Jul 07 04:51:33 PM PDT 24
Finished Jul 07 04:51:42 PM PDT 24
Peak memory 217212 kb
Host smart-5e9a345d-7e8e-40fb-a14d-ae267c96459d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094930948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.4094930948
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2382376667
Short name T314
Test name
Test status
Simulation time 5010693634 ps
CPU time 177.52 seconds
Started Jul 07 04:51:31 PM PDT 24
Finished Jul 07 04:54:29 PM PDT 24
Peak memory 218864 kb
Host smart-b7fe0592-0110-4159-a710-57bf1a2cdfe9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382376667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2382376667
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1610184997
Short name T160
Test name
Test status
Simulation time 23266251694 ps
CPU time 54.74 seconds
Started Jul 07 04:51:31 PM PDT 24
Finished Jul 07 04:52:26 PM PDT 24
Peak memory 219244 kb
Host smart-cf64d069-3a5b-4a64-b73e-7f38c884cdfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610184997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1610184997
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2940239071
Short name T182
Test name
Test status
Simulation time 4420473363 ps
CPU time 34.47 seconds
Started Jul 07 04:51:34 PM PDT 24
Finished Jul 07 04:52:09 PM PDT 24
Peak memory 212008 kb
Host smart-0107b36d-cdb8-451a-aa74-5fe721ef3baf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2940239071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2940239071
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2120583101
Short name T355
Test name
Test status
Simulation time 355118380 ps
CPU time 19.88 seconds
Started Jul 07 04:51:30 PM PDT 24
Finished Jul 07 04:51:51 PM PDT 24
Peak memory 216284 kb
Host smart-e56ac98b-fbfc-4876-8718-5d7429f4482e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120583101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2120583101
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.872434582
Short name T198
Test name
Test status
Simulation time 406332641 ps
CPU time 30.27 seconds
Started Jul 07 04:51:32 PM PDT 24
Finished Jul 07 04:52:02 PM PDT 24
Peak memory 219208 kb
Host smart-3293b2b1-fdcf-4372-a7a3-db2ddaca50e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872434582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.872434582
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2218968464
Short name T262
Test name
Test status
Simulation time 21680013799 ps
CPU time 23.48 seconds
Started Jul 07 04:51:32 PM PDT 24
Finished Jul 07 04:51:55 PM PDT 24
Peak memory 217504 kb
Host smart-a6317411-3768-4646-b537-f4c49ab3a8f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218968464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2218968464
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.908913392
Short name T145
Test name
Test status
Simulation time 8347524452 ps
CPU time 120.53 seconds
Started Jul 07 04:51:31 PM PDT 24
Finished Jul 07 04:53:31 PM PDT 24
Peak memory 219488 kb
Host smart-2fbbcbbf-219f-48f2-963a-6c282a86eb0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908913392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.908913392
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1998976367
Short name T168
Test name
Test status
Simulation time 534247639 ps
CPU time 19.77 seconds
Started Jul 07 04:51:37 PM PDT 24
Finished Jul 07 04:51:57 PM PDT 24
Peak memory 219236 kb
Host smart-a4a32b77-ff2c-45a5-b7bf-96391b07d6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998976367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1998976367
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3082090578
Short name T238
Test name
Test status
Simulation time 6864816300 ps
CPU time 21.09 seconds
Started Jul 07 04:51:38 PM PDT 24
Finished Jul 07 04:52:00 PM PDT 24
Peak memory 217600 kb
Host smart-01b5c9b5-a506-4840-a106-9a1814bd25a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3082090578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3082090578
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.124900526
Short name T51
Test name
Test status
Simulation time 1721886872 ps
CPU time 20.84 seconds
Started Jul 07 04:51:32 PM PDT 24
Finished Jul 07 04:51:53 PM PDT 24
Peak memory 216064 kb
Host smart-c7cc6514-5327-4f30-a170-43ca616506c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124900526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.124900526
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1187567252
Short name T60
Test name
Test status
Simulation time 3668099443 ps
CPU time 42 seconds
Started Jul 07 04:51:30 PM PDT 24
Finished Jul 07 04:52:12 PM PDT 24
Peak memory 219184 kb
Host smart-704ea82a-5ea1-4b77-96c0-0b1793f34a27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187567252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1187567252
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1659344710
Short name T64
Test name
Test status
Simulation time 352930681 ps
CPU time 8.27 seconds
Started Jul 07 04:51:45 PM PDT 24
Finished Jul 07 04:51:53 PM PDT 24
Peak memory 216960 kb
Host smart-d62f36e4-b438-46ed-bb2e-75fc88541f99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659344710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1659344710
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2457954760
Short name T330
Test name
Test status
Simulation time 50257703645 ps
CPU time 458.08 seconds
Started Jul 07 04:51:35 PM PDT 24
Finished Jul 07 04:59:13 PM PDT 24
Peak memory 233928 kb
Host smart-2b385cf5-2f45-4c69-b707-ed8e8faf366f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457954760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2457954760
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2091803468
Short name T154
Test name
Test status
Simulation time 34928500248 ps
CPU time 51.26 seconds
Started Jul 07 04:51:40 PM PDT 24
Finished Jul 07 04:52:32 PM PDT 24
Peak memory 219140 kb
Host smart-398f928e-decc-4056-9bb6-53a2adf3da78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091803468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2091803468
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3500805277
Short name T294
Test name
Test status
Simulation time 2602065376 ps
CPU time 13.52 seconds
Started Jul 07 04:51:36 PM PDT 24
Finished Jul 07 04:51:50 PM PDT 24
Peak memory 218952 kb
Host smart-30fba5f5-a74f-4f2e-b048-85deec7d3066
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3500805277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3500805277
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.3667269929
Short name T11
Test name
Test status
Simulation time 4664493046 ps
CPU time 56.37 seconds
Started Jul 07 04:51:36 PM PDT 24
Finished Jul 07 04:52:33 PM PDT 24
Peak memory 216224 kb
Host smart-2cf3242f-559b-4689-94b7-6aea2e5c1368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667269929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.3667269929
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2548157178
Short name T167
Test name
Test status
Simulation time 47954595813 ps
CPU time 152.88 seconds
Started Jul 07 04:51:35 PM PDT 24
Finished Jul 07 04:54:08 PM PDT 24
Peak memory 219520 kb
Host smart-90d6cb67-0c54-470a-bcd5-786b7ca1eb9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548157178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2548157178
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.938028876
Short name T131
Test name
Test status
Simulation time 609025946 ps
CPU time 12.56 seconds
Started Jul 07 04:51:45 PM PDT 24
Finished Jul 07 04:51:58 PM PDT 24
Peak memory 217116 kb
Host smart-a3cf2eb9-7959-4065-ac5f-790f4419c39d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938028876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.938028876
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.409086091
Short name T227
Test name
Test status
Simulation time 49525710204 ps
CPU time 459.2 seconds
Started Jul 07 04:51:42 PM PDT 24
Finished Jul 07 04:59:21 PM PDT 24
Peak memory 239100 kb
Host smart-59c64c1f-a8b3-4778-bf41-07ae8f4469ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409086091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.409086091
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1091891072
Short name T10
Test name
Test status
Simulation time 11536224559 ps
CPU time 48.15 seconds
Started Jul 07 04:51:39 PM PDT 24
Finished Jul 07 04:52:27 PM PDT 24
Peak memory 219284 kb
Host smart-65eb3114-69d8-4f4e-9d94-2e25161b2766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091891072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1091891072
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1345709640
Short name T348
Test name
Test status
Simulation time 4556232679 ps
CPU time 13.72 seconds
Started Jul 07 04:51:44 PM PDT 24
Finished Jul 07 04:51:58 PM PDT 24
Peak memory 219276 kb
Host smart-08eedbe2-3259-49f5-a4db-82873386739e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1345709640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1345709640
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1514069002
Short name T189
Test name
Test status
Simulation time 6603950558 ps
CPU time 64.3 seconds
Started Jul 07 04:51:43 PM PDT 24
Finished Jul 07 04:52:48 PM PDT 24
Peak memory 216800 kb
Host smart-3a229734-dd1b-46f5-af82-b6e86e86e846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514069002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1514069002
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2267950665
Short name T172
Test name
Test status
Simulation time 18189872548 ps
CPU time 100.96 seconds
Started Jul 07 04:51:42 PM PDT 24
Finished Jul 07 04:53:23 PM PDT 24
Peak memory 219268 kb
Host smart-a3e28250-a91f-4a02-abee-c4500bcef251
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267950665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2267950665
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1031345001
Short name T356
Test name
Test status
Simulation time 16336834510 ps
CPU time 33.39 seconds
Started Jul 07 04:51:45 PM PDT 24
Finished Jul 07 04:52:19 PM PDT 24
Peak memory 217376 kb
Host smart-d0496c1a-d58a-4496-8ee7-141d65c7c67f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031345001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1031345001
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1568385375
Short name T284
Test name
Test status
Simulation time 53179977340 ps
CPU time 616.71 seconds
Started Jul 07 04:51:43 PM PDT 24
Finished Jul 07 05:02:00 PM PDT 24
Peak memory 217964 kb
Host smart-75d12112-3016-4336-b88c-77759f32b161
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568385375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1568385375
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.353069850
Short name T155
Test name
Test status
Simulation time 369702914 ps
CPU time 10.88 seconds
Started Jul 07 04:51:43 PM PDT 24
Finished Jul 07 04:51:54 PM PDT 24
Peak memory 219204 kb
Host smart-a52183b9-b966-4ae5-af72-8534287cdc03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=353069850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.353069850
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3330970921
Short name T350
Test name
Test status
Simulation time 1491922673 ps
CPU time 29.73 seconds
Started Jul 07 04:51:44 PM PDT 24
Finished Jul 07 04:52:14 PM PDT 24
Peak memory 216304 kb
Host smart-ba8c0ead-0b64-4449-919c-63a49497f2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330970921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3330970921
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2640124903
Short name T220
Test name
Test status
Simulation time 1545412507 ps
CPU time 28.93 seconds
Started Jul 07 04:51:41 PM PDT 24
Finished Jul 07 04:52:10 PM PDT 24
Peak memory 219324 kb
Host smart-59f1daf1-ea5c-4799-8cbd-f7d84f9cc16d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640124903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2640124903
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.326461047
Short name T32
Test name
Test status
Simulation time 11889765038 ps
CPU time 243.58 seconds
Started Jul 07 04:51:47 PM PDT 24
Finished Jul 07 04:55:51 PM PDT 24
Peak memory 228512 kb
Host smart-ed06a29f-398a-4add-98a2-7fd0d00757ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326461047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.326461047
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.53033470
Short name T117
Test name
Test status
Simulation time 26248828683 ps
CPU time 60.95 seconds
Started Jul 07 04:51:47 PM PDT 24
Finished Jul 07 04:52:48 PM PDT 24
Peak memory 219176 kb
Host smart-d7e072f0-98f5-4a40-a831-06cddc05f787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53033470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.53033470
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2043421665
Short name T217
Test name
Test status
Simulation time 9247658080 ps
CPU time 25.1 seconds
Started Jul 07 04:51:47 PM PDT 24
Finished Jul 07 04:52:12 PM PDT 24
Peak memory 212036 kb
Host smart-28fb2483-e97c-46d0-b472-df76ba870394
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2043421665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2043421665
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.3874791621
Short name T245
Test name
Test status
Simulation time 348872971 ps
CPU time 20.06 seconds
Started Jul 07 04:51:51 PM PDT 24
Finished Jul 07 04:52:12 PM PDT 24
Peak memory 215876 kb
Host smart-df1fdb19-35a2-4793-8c87-630c96039641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874791621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.3874791621
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.294660636
Short name T193
Test name
Test status
Simulation time 1576643804 ps
CPU time 26.83 seconds
Started Jul 07 04:51:48 PM PDT 24
Finished Jul 07 04:52:15 PM PDT 24
Peak memory 219148 kb
Host smart-2c7d2ffc-df9a-4d86-bf42-f998b3f02598
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294660636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.294660636
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.270953387
Short name T127
Test name
Test status
Simulation time 338428356 ps
CPU time 8.36 seconds
Started Jul 07 04:51:54 PM PDT 24
Finished Jul 07 04:52:03 PM PDT 24
Peak memory 216952 kb
Host smart-cc730483-84c6-4ea2-84b9-19be826d5691
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270953387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.270953387
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1650262010
Short name T225
Test name
Test status
Simulation time 51388207188 ps
CPU time 489.15 seconds
Started Jul 07 04:51:51 PM PDT 24
Finished Jul 07 05:00:00 PM PDT 24
Peak memory 241292 kb
Host smart-d7a93f66-cc31-4636-9310-e88327428d94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650262010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1650262010
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1503388241
Short name T143
Test name
Test status
Simulation time 3913546575 ps
CPU time 43.99 seconds
Started Jul 07 04:51:52 PM PDT 24
Finished Jul 07 04:52:36 PM PDT 24
Peak memory 219260 kb
Host smart-4e51c9e6-fb52-41b0-8686-2dadc36a026f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503388241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1503388241
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.67051623
Short name T173
Test name
Test status
Simulation time 354784964 ps
CPU time 10.51 seconds
Started Jul 07 04:51:47 PM PDT 24
Finished Jul 07 04:51:58 PM PDT 24
Peak memory 219240 kb
Host smart-8ead9b9e-6827-40ab-a789-5ad4e59a11ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=67051623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.67051623
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.3278332764
Short name T206
Test name
Test status
Simulation time 43703676566 ps
CPU time 64.54 seconds
Started Jul 07 04:51:46 PM PDT 24
Finished Jul 07 04:52:51 PM PDT 24
Peak memory 217476 kb
Host smart-87ecb4b5-63bb-4c3e-a605-1bfa4292672e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278332764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.3278332764
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2786833834
Short name T157
Test name
Test status
Simulation time 1058053408 ps
CPU time 15.96 seconds
Started Jul 07 04:51:47 PM PDT 24
Finished Jul 07 04:52:03 PM PDT 24
Peak memory 219204 kb
Host smart-c87f2d41-cb4d-48c1-ad84-fbef8128a004
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786833834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2786833834
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2702934821
Short name T27
Test name
Test status
Simulation time 169379567 ps
CPU time 8.58 seconds
Started Jul 07 04:51:52 PM PDT 24
Finished Jul 07 04:52:01 PM PDT 24
Peak memory 217012 kb
Host smart-a9b61ff0-5478-41a7-97bb-417731774a66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702934821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2702934821
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.402013858
Short name T184
Test name
Test status
Simulation time 2395213878 ps
CPU time 184.14 seconds
Started Jul 07 04:51:51 PM PDT 24
Finished Jul 07 04:54:55 PM PDT 24
Peak memory 242152 kb
Host smart-556dbb96-4a80-4eaa-898e-eb3b2f7f00db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402013858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.402013858
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1949842675
Short name T344
Test name
Test status
Simulation time 332793230 ps
CPU time 20.18 seconds
Started Jul 07 04:51:51 PM PDT 24
Finished Jul 07 04:52:11 PM PDT 24
Peak memory 219120 kb
Host smart-1a930dc4-ee08-48a2-aab6-66fa71d695be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949842675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1949842675
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3203919082
Short name T310
Test name
Test status
Simulation time 21857063497 ps
CPU time 30.83 seconds
Started Jul 07 04:51:51 PM PDT 24
Finished Jul 07 04:52:22 PM PDT 24
Peak memory 219652 kb
Host smart-57cf7416-79d8-4a11-ab1d-d64dcc218289
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3203919082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3203919082
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3828200062
Short name T263
Test name
Test status
Simulation time 17217129217 ps
CPU time 132.53 seconds
Started Jul 07 04:51:51 PM PDT 24
Finished Jul 07 04:54:04 PM PDT 24
Peak memory 227560 kb
Host smart-2a5126d6-25eb-426d-8447-6167b5a8c6e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828200062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3828200062
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2619562211
Short name T340
Test name
Test status
Simulation time 9911984655 ps
CPU time 23.34 seconds
Started Jul 07 04:50:13 PM PDT 24
Finished Jul 07 04:50:37 PM PDT 24
Peak memory 217396 kb
Host smart-40d4845c-1f10-4af5-be86-01a42d001845
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619562211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2619562211
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3790169111
Short name T327
Test name
Test status
Simulation time 2922588753 ps
CPU time 186.3 seconds
Started Jul 07 04:50:13 PM PDT 24
Finished Jul 07 04:53:20 PM PDT 24
Peak memory 230644 kb
Host smart-ad0df88b-6fd6-4449-949d-9da4ded88056
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790169111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3790169111
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.400295355
Short name T5
Test name
Test status
Simulation time 29137654312 ps
CPU time 67.43 seconds
Started Jul 07 04:50:12 PM PDT 24
Finished Jul 07 04:51:20 PM PDT 24
Peak memory 219168 kb
Host smart-28e43edf-1a62-426d-996d-e01c484f54b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400295355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.400295355
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2013757583
Short name T246
Test name
Test status
Simulation time 71232176800 ps
CPU time 36.39 seconds
Started Jul 07 04:50:12 PM PDT 24
Finished Jul 07 04:50:49 PM PDT 24
Peak memory 217628 kb
Host smart-edc616e8-33b7-4fc2-91e5-03ec45c3b500
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2013757583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2013757583
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1253873174
Short name T218
Test name
Test status
Simulation time 6484549190 ps
CPU time 71.27 seconds
Started Jul 07 04:50:12 PM PDT 24
Finished Jul 07 04:51:23 PM PDT 24
Peak memory 215896 kb
Host smart-b45d50b4-51c6-4586-abc9-b29181643155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253873174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1253873174
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3594388885
Short name T260
Test name
Test status
Simulation time 5726360206 ps
CPU time 17.47 seconds
Started Jul 07 04:50:13 PM PDT 24
Finished Jul 07 04:50:31 PM PDT 24
Peak memory 214532 kb
Host smart-6d454077-ad8c-4c19-a479-a49a57d58f79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594388885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3594388885
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.695611771
Short name T49
Test name
Test status
Simulation time 147586380804 ps
CPU time 2814.04 seconds
Started Jul 07 04:50:23 PM PDT 24
Finished Jul 07 05:37:17 PM PDT 24
Peak memory 252144 kb
Host smart-63030b77-145f-4c10-b2a9-2d13625dc3f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695611771 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.695611771
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1072434771
Short name T63
Test name
Test status
Simulation time 899932516 ps
CPU time 14.72 seconds
Started Jul 07 04:50:12 PM PDT 24
Finished Jul 07 04:50:27 PM PDT 24
Peak memory 217004 kb
Host smart-565704e8-6ab8-46ea-a010-bbd4ff539288
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072434771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1072434771
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3026372780
Short name T196
Test name
Test status
Simulation time 4748338235 ps
CPU time 324.36 seconds
Started Jul 07 04:50:23 PM PDT 24
Finished Jul 07 04:55:48 PM PDT 24
Peak memory 240424 kb
Host smart-3dd8f882-1586-4672-906f-c585d9a5bf09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026372780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3026372780
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1769575422
Short name T331
Test name
Test status
Simulation time 1270646893 ps
CPU time 19.4 seconds
Started Jul 07 04:50:11 PM PDT 24
Finished Jul 07 04:50:30 PM PDT 24
Peak memory 219236 kb
Host smart-a425519f-c546-4a91-8d65-546680110852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769575422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1769575422
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3335960635
Short name T267
Test name
Test status
Simulation time 354737958 ps
CPU time 10.42 seconds
Started Jul 07 04:50:12 PM PDT 24
Finished Jul 07 04:50:23 PM PDT 24
Peak memory 219176 kb
Host smart-63a0ff0f-6023-4e85-a305-e7dadd0f300a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3335960635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3335960635
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3569104619
Short name T269
Test name
Test status
Simulation time 8248846085 ps
CPU time 65.88 seconds
Started Jul 07 04:50:15 PM PDT 24
Finished Jul 07 04:51:21 PM PDT 24
Peak memory 217312 kb
Host smart-c93229f7-e9f2-4739-8f81-e87ca67a779a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569104619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3569104619
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2455233206
Short name T176
Test name
Test status
Simulation time 670730863 ps
CPU time 35.01 seconds
Started Jul 07 04:50:15 PM PDT 24
Finished Jul 07 04:50:50 PM PDT 24
Peak memory 219228 kb
Host smart-4a9e8dd3-29ba-4765-a7b5-fec3d8c5a611
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455233206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2455233206
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2119775607
Short name T208
Test name
Test status
Simulation time 13971334543 ps
CPU time 22.88 seconds
Started Jul 07 04:50:20 PM PDT 24
Finished Jul 07 04:50:43 PM PDT 24
Peak memory 217344 kb
Host smart-227f26a9-cef1-44c2-8c50-f6a6d4191629
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119775607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2119775607
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2031147292
Short name T252
Test name
Test status
Simulation time 204393484877 ps
CPU time 654.48 seconds
Started Jul 07 04:50:14 PM PDT 24
Finished Jul 07 05:01:09 PM PDT 24
Peak memory 240184 kb
Host smart-bd533ad2-cbf7-4a43-8f0a-cfc7c6642e8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031147292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2031147292
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2755558963
Short name T240
Test name
Test status
Simulation time 9670831435 ps
CPU time 69.98 seconds
Started Jul 07 04:50:23 PM PDT 24
Finished Jul 07 04:51:33 PM PDT 24
Peak memory 219316 kb
Host smart-ef6fca6e-e793-4b7d-94f9-1a109c80c3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755558963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2755558963
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2564540561
Short name T320
Test name
Test status
Simulation time 11870834064 ps
CPU time 23.33 seconds
Started Jul 07 04:50:11 PM PDT 24
Finished Jul 07 04:50:35 PM PDT 24
Peak memory 219268 kb
Host smart-474fcfac-c518-4ca7-9b6c-ab97c7ed70bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2564540561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2564540561
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.417690137
Short name T179
Test name
Test status
Simulation time 20377220941 ps
CPU time 51.87 seconds
Started Jul 07 04:50:14 PM PDT 24
Finished Jul 07 04:51:06 PM PDT 24
Peak memory 215932 kb
Host smart-2b5d8054-209d-4c7a-a8a3-47f96a5bbb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417690137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.417690137
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1204131754
Short name T201
Test name
Test status
Simulation time 22675767094 ps
CPU time 255.32 seconds
Started Jul 07 04:50:13 PM PDT 24
Finished Jul 07 04:54:29 PM PDT 24
Peak memory 227468 kb
Host smart-3e0ab4fb-1e6d-4d13-8a8b-637c954026cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204131754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1204131754
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.4069468466
Short name T305
Test name
Test status
Simulation time 2062037291 ps
CPU time 8.6 seconds
Started Jul 07 04:50:19 PM PDT 24
Finished Jul 07 04:50:28 PM PDT 24
Peak memory 217012 kb
Host smart-22e9dccb-5268-4443-9174-4353e9059797
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069468466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.4069468466
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3014845410
Short name T197
Test name
Test status
Simulation time 252196520077 ps
CPU time 625.13 seconds
Started Jul 07 04:50:19 PM PDT 24
Finished Jul 07 05:00:44 PM PDT 24
Peak memory 233800 kb
Host smart-99cda3c0-4d0a-49e3-94c9-242812b3351f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014845410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3014845410
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2948239021
Short name T158
Test name
Test status
Simulation time 333464509 ps
CPU time 19.53 seconds
Started Jul 07 04:50:17 PM PDT 24
Finished Jul 07 04:50:37 PM PDT 24
Peak memory 219212 kb
Host smart-82b156a4-237e-448a-bdfe-c0ac185e1310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948239021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2948239021
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1811191989
Short name T307
Test name
Test status
Simulation time 5169860520 ps
CPU time 18.16 seconds
Started Jul 07 04:50:18 PM PDT 24
Finished Jul 07 04:50:37 PM PDT 24
Peak memory 211984 kb
Host smart-29d12f48-c56a-40cc-89d4-3af137866fee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1811191989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1811191989
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.241395718
Short name T43
Test name
Test status
Simulation time 17883397773 ps
CPU time 46.56 seconds
Started Jul 07 04:50:17 PM PDT 24
Finished Jul 07 04:51:04 PM PDT 24
Peak memory 216244 kb
Host smart-153bbf99-ca52-41b8-a6fa-c2d8c9f07d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241395718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.241395718
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.602727684
Short name T234
Test name
Test status
Simulation time 5368344734 ps
CPU time 34.43 seconds
Started Jul 07 04:50:18 PM PDT 24
Finished Jul 07 04:50:52 PM PDT 24
Peak memory 218800 kb
Host smart-088ca0f0-9680-4031-9a02-36fbf1c9dcad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602727684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.rom_ctrl_stress_all.602727684
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1712064499
Short name T194
Test name
Test status
Simulation time 3333518168 ps
CPU time 18.85 seconds
Started Jul 07 04:50:23 PM PDT 24
Finished Jul 07 04:50:42 PM PDT 24
Peak memory 217216 kb
Host smart-c8c1ab54-3cfd-4322-8509-29dbc105910c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712064499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1712064499
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1273676113
Short name T38
Test name
Test status
Simulation time 394009544695 ps
CPU time 495.93 seconds
Started Jul 07 04:50:18 PM PDT 24
Finished Jul 07 04:58:34 PM PDT 24
Peak memory 233776 kb
Host smart-44f7e233-56a3-4edf-a788-51cabee1e3b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273676113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1273676113
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.980649186
Short name T306
Test name
Test status
Simulation time 20559941684 ps
CPU time 50.85 seconds
Started Jul 07 04:50:18 PM PDT 24
Finished Jul 07 04:51:09 PM PDT 24
Peak memory 219296 kb
Host smart-20f916af-547b-4a0a-86de-fa76cb95fe6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980649186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.980649186
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.576930212
Short name T312
Test name
Test status
Simulation time 1486177872 ps
CPU time 19.53 seconds
Started Jul 07 04:50:18 PM PDT 24
Finished Jul 07 04:50:38 PM PDT 24
Peak memory 211616 kb
Host smart-fbb9cd9b-f898-403f-9a32-37165990d180
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=576930212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.576930212
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.4127006809
Short name T166
Test name
Test status
Simulation time 1385110652 ps
CPU time 20.39 seconds
Started Jul 07 04:50:16 PM PDT 24
Finished Jul 07 04:50:37 PM PDT 24
Peak memory 216260 kb
Host smart-25566756-36c0-4d06-b677-3a4895ae7a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127006809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.4127006809
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2725300356
Short name T7
Test name
Test status
Simulation time 27391233845 ps
CPU time 32.32 seconds
Started Jul 07 04:50:23 PM PDT 24
Finished Jul 07 04:50:56 PM PDT 24
Peak memory 219160 kb
Host smart-2515d029-bc14-4cae-ba5f-21c3b00941a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725300356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2725300356
Directory /workspace/9.rom_ctrl_stress_all/latest
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