Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 35659 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 464280 1 T1 10 T2 3 T3 7



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 144240 1 T1 129 T2 55 T3 115
values[0x0] 174706 1 T14 29732 T15 24927 T16 37706
values[0x1] 180993 1 T14 30755 T15 25935 T16 39256



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 17172 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 482767 1 T1 76 T2 28 T3 62



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 1860 1 T103 7 T121 2 T65 6
valid_sources[0x01] 2048 1 T1 2 T5 27 T18 1
valid_sources[0x02] 1895 1 T4 10 T6 1 T9 1
valid_sources[0x03] 1844 1 T1 1 T3 1 T14 300
valid_sources[0x04] 1897 1 T3 2 T9 1 T78 5
valid_sources[0x05] 1908 1 T8 1 T121 3 T66 1
valid_sources[0x06] 1944 1 T1 2 T2 4 T10 3
valid_sources[0x07] 1899 1 T4 3 T18 3 T121 2
valid_sources[0x08] 2025 1 T1 1 T3 3 T9 1
valid_sources[0x09] 2100 1 T1 1 T78 14 T121 1
valid_sources[0x0a] 1880 1 T13 4 T121 2 T122 1
valid_sources[0x0b] 1989 1 T9 3 T10 1 T66 2
valid_sources[0x0c] 1899 1 T123 3 T80 1 T121 2
valid_sources[0x0d] 1933 1 T8 2 T12 6 T103 4
valid_sources[0x0e] 1988 1 T9 2 T78 4 T14 304
valid_sources[0x0f] 1969 1 T3 4 T12 7 T80 1
valid_sources[0x10] 1829 1 T6 1 T9 1 T121 1
valid_sources[0x11] 2126 1 T1 3 T9 1 T44 2
valid_sources[0x12] 1842 1 T2 2 T6 1 T9 3
valid_sources[0x13] 1802 1 T1 1 T3 1 T12 3
valid_sources[0x14] 1952 1 T1 1 T2 9 T103 2
valid_sources[0x15] 1926 1 T1 1 T3 2 T8 1
valid_sources[0x16] 2022 1 T1 1 T4 6 T9 1
valid_sources[0x17] 1955 1 T9 1 T10 2 T44 1
valid_sources[0x18] 1978 1 T3 2 T9 1 T14 325
valid_sources[0x19] 2007 1 T78 6 T80 1 T66 2
valid_sources[0x1a] 1838 1 T2 2 T9 1 T44 2
valid_sources[0x1b] 1963 1 T6 1 T121 1 T14 328
valid_sources[0x1c] 2031 1 T3 1 T6 4 T9 2
valid_sources[0x1d] 1887 1 T1 3 T10 1 T78 2
valid_sources[0x1e] 1878 1 T1 1 T3 3 T8 1
valid_sources[0x1f] 1817 1 T4 16 T121 1 T65 2
valid_sources[0x20] 1948 1 T4 3 T9 1 T44 1
valid_sources[0x21] 2049 1 T1 1 T9 1 T79 1
valid_sources[0x22] 1937 1 T1 1 T79 1 T80 1
valid_sources[0x23] 1999 1 T2 1 T9 1 T18 1
valid_sources[0x24] 1912 1 T1 1 T4 2 T123 1
valid_sources[0x25] 1925 1 T1 1 T4 6 T6 1
valid_sources[0x26] 1958 1 T6 1 T12 4 T121 1
valid_sources[0x27] 1996 1 T8 1 T9 1 T13 1
valid_sources[0x28] 1988 1 T12 4 T14 329 T34 4
valid_sources[0x29] 1920 1 T3 1 T4 1 T12 7
valid_sources[0x2a] 2042 1 T1 3 T6 5 T9 2
valid_sources[0x2b] 1981 1 T4 1 T6 1 T121 1
valid_sources[0x2c] 1904 1 T5 32 T10 1 T18 6
valid_sources[0x2d] 1991 1 T1 1 T3 1 T4 1
valid_sources[0x2e] 2037 1 T9 1 T78 3 T121 1
valid_sources[0x2f] 1840 1 T1 1 T6 2 T103 2
valid_sources[0x30] 1891 1 T3 1 T9 1 T10 1
valid_sources[0x31] 1814 1 T13 2 T78 1 T66 1
valid_sources[0x32] 2047 1 T3 3 T8 1 T9 2
valid_sources[0x33] 1964 1 T8 1 T9 2 T43 14
valid_sources[0x34] 1939 1 T8 3 T121 1 T122 1
valid_sources[0x35] 1887 1 T2 2 T4 4 T9 1
valid_sources[0x36] 2059 1 T3 1 T8 1 T9 2
valid_sources[0x37] 2138 1 T6 1 T9 1 T10 1
valid_sources[0x38] 1841 1 T2 1 T9 1 T10 1
valid_sources[0x39] 2067 1 T1 1 T8 1 T9 1
valid_sources[0x3a] 1896 1 T103 2 T79 4 T80 1
valid_sources[0x3b] 1884 1 T4 1 T6 1 T13 1
valid_sources[0x3c] 1930 1 T9 1 T80 2 T121 1
valid_sources[0x3d] 1865 1 T4 5 T9 1 T12 1
valid_sources[0x3e] 1925 1 T1 2 T3 1 T10 1
valid_sources[0x3f] 2029 1 T3 1 T6 3 T9 2
valid_sources[0x40] 1992 1 T3 1 T8 2 T18 2
valid_sources[0x41] 1973 1 T3 1 T8 1 T9 2
valid_sources[0x42] 1951 1 T1 4 T2 1 T9 1
valid_sources[0x43] 1852 1 T9 1 T103 2 T121 2
valid_sources[0x44] 1982 1 T1 1 T3 1 T5 28
valid_sources[0x45] 1965 1 T2 1 T3 2 T4 1
valid_sources[0x46] 2044 1 T12 1 T123 1 T14 320
valid_sources[0x47] 1956 1 T3 2 T10 2 T13 5
valid_sources[0x48] 2047 1 T1 1 T6 1 T9 3
valid_sources[0x49] 1876 1 T2 2 T9 1 T78 5
valid_sources[0x4a] 1931 1 T1 1 T3 1 T78 2
valid_sources[0x4b] 1937 1 T1 1 T3 3 T6 1
valid_sources[0x4c] 1877 1 T1 2 T6 1 T12 3
valid_sources[0x4d] 2077 1 T9 1 T78 7 T80 2
valid_sources[0x4e] 2007 1 T4 2 T103 1 T13 3
valid_sources[0x4f] 1957 1 T3 2 T9 1 T10 1
valid_sources[0x50] 2175 1 T4 1 T6 1 T9 1
valid_sources[0x51] 1930 1 T6 1 T12 6 T44 2
valid_sources[0x52] 1933 1 T1 1 T2 2 T4 7
valid_sources[0x53] 1948 1 T3 2 T13 1 T122 3
valid_sources[0x54] 2022 1 T1 1 T2 1 T3 1
valid_sources[0x55] 2074 1 T1 1 T3 2 T103 2
valid_sources[0x56] 1964 1 T8 1 T9 1 T44 1
valid_sources[0x57] 1899 1 T1 1 T103 1 T13 2
valid_sources[0x58] 1990 1 T1 1 T3 1 T4 5
valid_sources[0x59] 2041 1 T44 3 T103 5 T79 3
valid_sources[0x5a] 1925 1 T3 3 T8 1 T103 2
valid_sources[0x5b] 1821 1 T4 14 T6 2 T123 6
valid_sources[0x5c] 2051 1 T3 1 T43 3 T79 2
valid_sources[0x5d] 2159 1 T1 2 T3 1 T9 4
valid_sources[0x5e] 1819 1 T4 12 T103 3 T123 1
valid_sources[0x5f] 1958 1 T1 1 T3 1 T9 1
valid_sources[0x60] 1946 1 T9 1 T10 1 T66 3
valid_sources[0x61] 1978 1 T9 2 T18 1 T44 1
valid_sources[0x62] 1933 1 T3 1 T9 2 T18 1
valid_sources[0x63] 1962 1 T1 1 T6 2 T9 2
valid_sources[0x64] 1922 1 T1 1 T9 1 T12 2
valid_sources[0x65] 1959 1 T1 1 T4 2 T80 1
valid_sources[0x66] 1842 1 T103 3 T122 1 T14 300
valid_sources[0x67] 1923 1 T103 2 T79 1 T123 4
valid_sources[0x68] 1966 1 T1 1 T80 1 T122 1
valid_sources[0x69] 1996 1 T3 2 T10 1 T78 7
valid_sources[0x6a] 1946 1 T9 3 T12 4 T103 1
valid_sources[0x6b] 2083 1 T1 1 T9 1 T44 2
valid_sources[0x6c] 1949 1 T3 1 T5 14 T8 1
valid_sources[0x6d] 1937 1 T1 1 T12 7 T103 1
valid_sources[0x6e] 1872 1 T1 2 T3 1 T6 2
valid_sources[0x6f] 1948 1 T103 1 T123 2 T66 2
valid_sources[0x70] 1844 1 T3 1 T4 3 T9 1
valid_sources[0x71] 2078 1 T3 1 T8 1 T9 1
valid_sources[0x72] 1878 1 T1 2 T6 3 T78 7
valid_sources[0x73] 1997 1 T2 2 T3 1 T12 2
valid_sources[0x74] 2010 1 T9 1 T43 3 T103 1
valid_sources[0x75] 1932 1 T1 1 T12 12 T103 1
valid_sources[0x76] 1950 1 T9 1 T80 1 T65 1
valid_sources[0x77] 1971 1 T1 1 T4 1 T18 2
valid_sources[0x78] 2090 1 T6 1 T18 1 T78 2
valid_sources[0x79] 1986 1 T3 1 T10 3 T121 1
valid_sources[0x7a] 1995 1 T1 2 T4 2 T18 1
valid_sources[0x7b] 2009 1 T1 1 T8 2 T18 2
valid_sources[0x7c] 1968 1 T18 1 T12 1 T13 2
valid_sources[0x7d] 2082 1 T1 1 T2 1 T3 1
valid_sources[0x7e] 1920 1 T4 16 T78 7 T14 320
valid_sources[0x7f] 2012 1 T3 2 T6 1 T9 2
valid_sources[0x80] 1931 1 T1 1 T4 4 T9 2



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 118148 1 T1 10 T2 3 T3 7
values[0x0] all_enables biggest_size 173173 1 T14 29470 T15 24731 T16 37398
values[0x1] all_enables biggest_size 172959 1 T14 29407 T15 24884 T16 37543


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 41240 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 371753 1 T2 11 T4 67 T6 19



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 107055 1 T2 32 T4 128 T6 32
values[0x0] 141889 1 T25 9 T26 3 T14 23617
values[0x1] 164049 1 T25 6 T26 6 T14 27342



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 20553 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 392440 1 T2 15 T4 76 T6 22



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 1607 1 T4 1 T25 1 T14 216
valid_sources[0x01] 1573 1 T13 1 T105 1 T14 268
valid_sources[0x02] 1636 1 T6 2 T14 308 T124 2
valid_sources[0x03] 1655 1 T4 1 T14 262 T125 2
valid_sources[0x04] 1658 1 T4 1 T14 269 T81 1
valid_sources[0x05] 1561 1 T103 1 T14 224 T126 4
valid_sources[0x06] 1613 1 T4 1 T14 268 T34 1
valid_sources[0x07] 1550 1 T4 1 T14 303 T127 1
valid_sources[0x08] 1558 1 T4 1 T40 1 T14 236
valid_sources[0x09] 1631 1 T14 273 T128 3 T129 2
valid_sources[0x0a] 1565 1 T14 249 T130 1 T131 1
valid_sources[0x0b] 1674 1 T105 2 T14 318 T33 21
valid_sources[0x0c] 1647 1 T14 312 T127 1 T124 1
valid_sources[0x0d] 1581 1 T105 2 T14 259 T132 1
valid_sources[0x0e] 1535 1 T6 1 T20 1 T14 239
valid_sources[0x0f] 1676 1 T8 32 T14 302 T34 1
valid_sources[0x10] 1589 1 T6 1 T103 2 T105 2
valid_sources[0x11] 1626 1 T80 4 T14 290 T133 2
valid_sources[0x12] 1509 1 T103 2 T105 1 T14 269
valid_sources[0x13] 1505 1 T4 1 T103 3 T105 5
valid_sources[0x14] 1650 1 T14 232 T31 10 T129 1
valid_sources[0x15] 1586 1 T4 1 T80 1 T20 1
valid_sources[0x16] 1544 1 T4 1 T14 242 T134 3
valid_sources[0x17] 1691 1 T20 1 T14 292 T34 1
valid_sources[0x18] 1644 1 T4 1 T40 1 T14 258
valid_sources[0x19] 1547 1 T80 3 T14 221 T132 1
valid_sources[0x1a] 1806 1 T43 11 T14 310 T21 1
valid_sources[0x1b] 1589 1 T14 237 T124 1 T135 1
valid_sources[0x1c] 1630 1 T14 262 T125 2 T15 256
valid_sources[0x1d] 1727 1 T4 1 T80 1 T105 1
valid_sources[0x1e] 1568 1 T13 1 T105 1 T20 1
valid_sources[0x1f] 1452 1 T4 2 T105 2 T14 209
valid_sources[0x20] 1559 1 T4 1 T14 237 T136 1
valid_sources[0x21] 1741 1 T4 1 T14 237 T137 2
valid_sources[0x22] 1705 1 T4 2 T14 268 T15 238
valid_sources[0x23] 1546 1 T14 271 T138 1 T124 1
valid_sources[0x24] 1583 1 T4 2 T105 1 T14 252
valid_sources[0x25] 1556 1 T14 333 T124 2 T139 1
valid_sources[0x26] 1769 1 T4 1 T14 270 T125 1
valid_sources[0x27] 1621 1 T4 2 T14 224 T81 1
valid_sources[0x28] 1627 1 T14 265 T130 1 T131 1
valid_sources[0x29] 1653 1 T2 2 T14 245 T140 2
valid_sources[0x2a] 1672 1 T13 1 T80 1 T26 1
valid_sources[0x2b] 1809 1 T40 1 T14 207 T141 6
valid_sources[0x2c] 1628 1 T10 1 T103 2 T14 273
valid_sources[0x2d] 1664 1 T13 1 T14 309 T125 1
valid_sources[0x2e] 1619 1 T6 1 T10 1 T12 64
valid_sources[0x2f] 1519 1 T10 1 T14 236 T39 3
valid_sources[0x30] 1548 1 T10 1 T14 269 T35 1
valid_sources[0x31] 1624 1 T4 2 T40 1 T14 321
valid_sources[0x32] 1673 1 T14 269 T35 1 T39 1
valid_sources[0x33] 1719 1 T2 1 T14 344 T81 3
valid_sources[0x34] 1627 1 T80 1 T14 284 T125 1
valid_sources[0x35] 1720 1 T103 2 T14 212 T34 1
valid_sources[0x36] 1617 1 T10 3 T14 236 T39 1
valid_sources[0x37] 1681 1 T80 1 T14 296 T142 2
valid_sources[0x38] 1671 1 T79 32 T80 2 T14 237
valid_sources[0x39] 1602 1 T2 1 T103 1 T14 287
valid_sources[0x3a] 1600 1 T2 1 T4 1 T6 1
valid_sources[0x3b] 1713 1 T10 2 T80 3 T26 1
valid_sources[0x3c] 1633 1 T4 1 T105 2 T14 262
valid_sources[0x3d] 1631 1 T14 286 T138 2 T143 3
valid_sources[0x3e] 1676 1 T14 310 T141 1 T128 4
valid_sources[0x3f] 1556 1 T14 243 T144 1 T145 1
valid_sources[0x40] 1554 1 T13 1 T14 225 T146 3
valid_sources[0x41] 1620 1 T2 1 T4 1 T105 2
valid_sources[0x42] 1525 1 T2 1 T14 323 T131 1
valid_sources[0x43] 1624 1 T2 1 T10 2 T103 9
valid_sources[0x44] 1562 1 T103 1 T13 1 T105 1
valid_sources[0x45] 1605 1 T103 2 T13 1 T25 4
valid_sources[0x46] 1554 1 T4 1 T14 281 T139 1
valid_sources[0x47] 1634 1 T4 2 T103 1 T14 266
valid_sources[0x48] 1639 1 T105 1 T14 243 T39 1
valid_sources[0x49] 1606 1 T4 1 T105 1 T14 276
valid_sources[0x4a] 1647 1 T14 291 T147 1 T132 1
valid_sources[0x4b] 1471 1 T4 1 T25 1 T14 213
valid_sources[0x4c] 1692 1 T4 1 T13 1 T105 1
valid_sources[0x4d] 1585 1 T13 2 T14 242 T39 1
valid_sources[0x4e] 1549 1 T2 1 T4 2 T6 1
valid_sources[0x4f] 1582 1 T26 1 T14 288 T33 3
valid_sources[0x50] 1591 1 T10 1 T14 306 T15 207
valid_sources[0x51] 1646 1 T4 1 T14 253 T144 1
valid_sources[0x52] 1668 1 T2 1 T10 1 T103 5
valid_sources[0x53] 1453 1 T80 1 T28 1 T14 221
valid_sources[0x54] 1639 1 T4 1 T80 2 T105 1
valid_sources[0x55] 1599 1 T4 1 T6 2 T103 1
valid_sources[0x56] 1531 1 T2 1 T4 1 T14 270
valid_sources[0x57] 1729 1 T4 4 T40 1 T14 326
valid_sources[0x58] 1637 1 T103 1 T14 260 T35 1
valid_sources[0x59] 1585 1 T2 1 T14 249 T81 1
valid_sources[0x5a] 1561 1 T2 1 T13 1 T14 310
valid_sources[0x5b] 1647 1 T14 277 T48 3 T148 1
valid_sources[0x5c] 1606 1 T2 1 T14 255 T138 1
valid_sources[0x5d] 1619 1 T14 262 T34 1 T81 2
valid_sources[0x5e] 1555 1 T6 2 T105 2 T14 281
valid_sources[0x5f] 1652 1 T4 2 T103 2 T80 1
valid_sources[0x60] 1597 1 T4 1 T20 1 T14 279
valid_sources[0x61] 1641 1 T4 1 T6 1 T13 1
valid_sources[0x62] 1536 1 T4 1 T20 1 T14 218
valid_sources[0x63] 1514 1 T4 1 T13 1 T14 203
valid_sources[0x64] 1583 1 T4 1 T10 1 T103 3
valid_sources[0x65] 1590 1 T80 1 T40 1 T14 242
valid_sources[0x66] 1630 1 T20 1 T14 280 T145 1
valid_sources[0x67] 1588 1 T80 1 T14 292 T34 1
valid_sources[0x68] 1591 1 T14 271 T139 1 T15 194
valid_sources[0x69] 1580 1 T4 1 T80 5 T14 273
valid_sources[0x6a] 1692 1 T4 2 T13 1 T14 299
valid_sources[0x6b] 1732 1 T14 343 T81 2 T125 2
valid_sources[0x6c] 1568 1 T13 1 T14 303 T81 2
valid_sources[0x6d] 1663 1 T4 1 T10 1 T14 270
valid_sources[0x6e] 1568 1 T14 267 T31 1 T148 4
valid_sources[0x6f] 1575 1 T103 1 T14 242 T34 1
valid_sources[0x70] 1642 1 T4 2 T14 266 T48 4
valid_sources[0x71] 1539 1 T14 208 T133 3 T124 1
valid_sources[0x72] 1617 1 T14 216 T15 266 T149 32
valid_sources[0x73] 1523 1 T4 1 T105 2 T14 241
valid_sources[0x74] 1633 1 T14 241 T38 23 T143 1
valid_sources[0x75] 1543 1 T14 279 T21 1 T145 1
valid_sources[0x76] 1661 1 T14 282 T39 1 T150 5
valid_sources[0x77] 1528 1 T4 3 T20 1 T14 254
valid_sources[0x78] 1618 1 T4 1 T103 1 T80 1
valid_sources[0x79] 1677 1 T14 222 T131 1 T151 64
valid_sources[0x7a] 1511 1 T80 1 T14 227 T48 2
valid_sources[0x7b] 1632 1 T6 1 T14 291 T81 1
valid_sources[0x7c] 1585 1 T4 1 T14 243 T142 2
valid_sources[0x7d] 1668 1 T6 1 T103 2 T105 1
valid_sources[0x7e] 1595 1 T14 274 T131 3 T144 2
valid_sources[0x7f] 1494 1 T2 1 T20 1 T14 233
valid_sources[0x80] 1640 1 T2 1 T10 1 T19 27



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 94714 1 T2 11 T4 67 T6 19
values[0x0] all_enables biggest_size 138494 1 T26 2 T14 23150 T35 1
values[0x1] all_enables biggest_size 138545 1 T25 1 T14 23069 T35 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%