Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

857740

1

T1

119

T2

52

T3

108

full_word

541305

1

T1

10

T2

3

T3

7

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1398745	1			T1	129		T2	55		T3	115
auto[TlIntgErrCmd]	105	1			T52	6		T54	8		T57	5
auto[TlIntgErrData]	99	1			T52	8		T54	1		T57	6
auto[TlIntgErrBoth]	96	1			T52	6		T54	1		T57	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

237568

1

T1

129

T2

55

T3

115

auto[1]

1161477

1

T14

199905

T15

160232

T16

246031

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	108120	1			T1	119		T2	52		T3	108
auto[TlIntgErrNone]	partial	auto[1]	749345	1			T14	129801		T15	101725		T16	157256
auto[TlIntgErrNone]	full_word	auto[0]	129309	1			T1	10		T2	3		T3	7
auto[TlIntgErrNone]	full_word	auto[1]	411971	1			T14	70104		T15	58507		T16	88775
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T52	3		T54	4		T57	4
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T52	2		T54	4		T57	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T113	2		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T52	1		T114	1		T115	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T52	2		T57	2		T107	2
auto[TlIntgErrData]	partial	auto[1]	42	1			T52	4		T54	1		T57	4
auto[TlIntgErrData]	full_word	auto[0]	4	1			T52	2		T114	1		T116	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T109	1		T117	1		T116	2
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T52	2		T54	1		T57	3
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T52	4		T57	5		T107	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T57	1		T114	1		T118	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T108	1		T112	2		T113	1