Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46692	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

824550

1

T3

41306

T5

17

T6

27

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	238370	1			T3	10943		T5	154		T6	309
values[0x0]	310859	1			T3	15715		T13	86546		T14	91290
values[0x1]	322013	1			T3	16155		T13	89829		T14	94604

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	23189	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

848053

1

T3

42008

T5

101

T6

186

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2972	1			T3	143		T18	1		T117	1
valid_sources[0x01]	4249	1			T3	135		T9	13		T117	1
valid_sources[0x02]	3114	1			T3	163		T11	1		T118	3
valid_sources[0x03]	3071	1			T3	206		T117	1		T96	5
valid_sources[0x04]	3612	1			T3	200		T95	5		T117	1
valid_sources[0x05]	3109	1			T3	128		T97	2		T71	1
valid_sources[0x06]	3092	1			T3	184		T118	3		T97	4
valid_sources[0x07]	3956	1			T3	177		T117	3		T119	1
valid_sources[0x08]	2935	1			T3	159		T19	4		T96	1
valid_sources[0x09]	3100	1			T3	165		T19	4		T117	1
valid_sources[0x0a]	3498	1			T3	159		T19	1		T95	8
valid_sources[0x0b]	3910	1			T3	168		T5	3		T117	2
valid_sources[0x0c]	4395	1			T3	176		T69	3		T117	1
valid_sources[0x0d]	3212	1			T3	130		T19	4		T95	1
valid_sources[0x0e]	3150	1			T3	128		T19	3		T95	1
valid_sources[0x0f]	4501	1			T3	160		T118	1		T97	1
valid_sources[0x10]	3060	1			T3	185		T5	1		T11	1
valid_sources[0x11]	3127	1			T3	137		T12	2		T117	2
valid_sources[0x12]	3327	1			T3	162		T16	23		T69	4
valid_sources[0x13]	3872	1			T3	152		T5	1		T96	6
valid_sources[0x14]	3223	1			T3	146		T19	2		T95	10
valid_sources[0x15]	3101	1			T3	142		T9	2		T19	3
valid_sources[0x16]	4034	1			T3	187		T19	2		T69	2
valid_sources[0x17]	3434	1			T3	142		T11	2		T18	14
valid_sources[0x18]	3091	1			T3	196		T5	1		T69	4
valid_sources[0x19]	3323	1			T3	134		T12	1		T96	2
valid_sources[0x1a]	3524	1			T3	151		T71	1		T99	3
valid_sources[0x1b]	3760	1			T3	195		T95	7		T120	26
valid_sources[0x1c]	3142	1			T3	175		T15	2		T96	4
valid_sources[0x1d]	3726	1			T3	183		T117	1		T97	2
valid_sources[0x1e]	3175	1			T3	157		T117	2		T96	1
valid_sources[0x1f]	4695	1			T3	208		T5	1		T18	1
valid_sources[0x20]	3157	1			T3	156		T5	1		T11	1
valid_sources[0x21]	3080	1			T3	164		T6	31		T9	1
valid_sources[0x22]	3188	1			T3	182		T117	2		T119	1
valid_sources[0x23]	3096	1			T3	168		T11	2		T18	15
valid_sources[0x24]	3961	1			T3	226		T95	7		T119	3
valid_sources[0x25]	3190	1			T3	164		T117	2		T96	8
valid_sources[0x26]	3459	1			T3	192		T19	2		T117	1
valid_sources[0x27]	3199	1			T3	153		T117	1		T119	1
valid_sources[0x28]	4002	1			T3	140		T5	3		T117	1
valid_sources[0x29]	3524	1			T3	210		T11	1		T19	1
valid_sources[0x2a]	3769	1			T3	142		T96	7		T100	1
valid_sources[0x2b]	3527	1			T3	173		T5	3		T6	99
valid_sources[0x2c]	3080	1			T3	181		T18	5		T118	1
valid_sources[0x2d]	3515	1			T3	116		T11	1		T97	1
valid_sources[0x2e]	3326	1			T3	173		T5	4		T11	1
valid_sources[0x2f]	3197	1			T3	156		T5	3		T11	1
valid_sources[0x30]	3042	1			T3	165		T71	4		T99	2
valid_sources[0x31]	3207	1			T3	148		T20	1		T117	1
valid_sources[0x32]	3104	1			T3	201		T5	1		T119	2
valid_sources[0x33]	3529	1			T3	154		T117	2		T96	1
valid_sources[0x34]	3100	1			T3	195		T5	1		T117	1
valid_sources[0x35]	3200	1			T3	234		T11	3		T121	38
valid_sources[0x36]	3416	1			T3	153		T5	4		T15	21
valid_sources[0x37]	3149	1			T3	131		T117	1		T96	2
valid_sources[0x38]	3487	1			T3	167		T5	4		T9	6
valid_sources[0x39]	3157	1			T3	199		T5	1		T69	2
valid_sources[0x3a]	3223	1			T3	148		T11	1		T18	4
valid_sources[0x3b]	3476	1			T3	144		T117	1		T119	1
valid_sources[0x3c]	3225	1			T3	134		T117	1		T118	2
valid_sources[0x3d]	3126	1			T3	169		T12	1		T117	1
valid_sources[0x3e]	2818	1			T3	137		T95	3		T117	1
valid_sources[0x3f]	3351	1			T3	184		T19	1		T96	3
valid_sources[0x40]	3440	1			T3	210		T118	1		T97	2
valid_sources[0x41]	3202	1			T3	145		T5	4		T117	1
valid_sources[0x42]	3124	1			T3	131		T19	1		T12	5
valid_sources[0x43]	2972	1			T3	156		T11	1		T96	2
valid_sources[0x44]	3059	1			T3	181		T117	2		T118	1
valid_sources[0x45]	3710	1			T3	136		T5	2		T117	1
valid_sources[0x46]	3400	1			T3	178		T5	2		T70	1
valid_sources[0x47]	3264	1			T3	171		T5	1		T18	7
valid_sources[0x48]	3093	1			T3	187		T5	1		T119	2
valid_sources[0x49]	3073	1			T3	146		T117	1		T118	3
valid_sources[0x4a]	3289	1			T3	174		T118	3		T97	1
valid_sources[0x4b]	4161	1			T3	187		T18	3		T12	3
valid_sources[0x4c]	3177	1			T3	188		T11	1		T18	1
valid_sources[0x4d]	3484	1			T3	166		T69	3		T96	1
valid_sources[0x4e]	3093	1			T3	130		T11	5		T117	1
valid_sources[0x4f]	3608	1			T3	160		T12	16		T96	4
valid_sources[0x50]	2955	1			T3	136		T5	3		T11	1
valid_sources[0x51]	3110	1			T3	181		T11	1		T95	6
valid_sources[0x52]	3676	1			T3	201		T5	1		T117	1
valid_sources[0x53]	4021	1			T3	141		T5	2		T11	1
valid_sources[0x54]	4403	1			T3	137		T19	1		T96	1
valid_sources[0x55]	4583	1			T3	170		T5	1		T15	6
valid_sources[0x56]	3130	1			T3	161		T11	5		T70	2
valid_sources[0x57]	3307	1			T3	197		T6	20		T18	2
valid_sources[0x58]	3146	1			T3	168		T5	2		T118	1
valid_sources[0x59]	3984	1			T3	147		T5	2		T9	6
valid_sources[0x5a]	3493	1			T3	181		T11	1		T117	1
valid_sources[0x5b]	3018	1			T3	161		T9	8		T20	1
valid_sources[0x5c]	3125	1			T3	155		T117	1		T118	3
valid_sources[0x5d]	3661	1			T3	173		T11	2		T95	2
valid_sources[0x5e]	3974	1			T3	122		T95	5		T96	2
valid_sources[0x5f]	3144	1			T3	168		T5	2		T117	3
valid_sources[0x60]	3207	1			T3	199		T70	3		T99	1
valid_sources[0x61]	3544	1			T3	201		T96	3		T118	3
valid_sources[0x62]	3558	1			T3	146		T5	2		T20	1
valid_sources[0x63]	3344	1			T3	221		T117	1		T97	1
valid_sources[0x64]	2992	1			T3	160		T5	1		T11	2
valid_sources[0x65]	3099	1			T3	135		T19	2		T96	2
valid_sources[0x66]	3136	1			T3	176		T5	2		T11	2
valid_sources[0x67]	3273	1			T3	156		T5	1		T16	11
valid_sources[0x68]	3210	1			T3	174		T11	1		T96	2
valid_sources[0x69]	3880	1			T3	197		T11	1		T18	4
valid_sources[0x6a]	3405	1			T3	199		T96	5		T119	1
valid_sources[0x6b]	3318	1			T3	134		T11	1		T118	1
valid_sources[0x6c]	2987	1			T3	197		T19	1		T69	1
valid_sources[0x6d]	3676	1			T3	193		T11	1		T18	16
valid_sources[0x6e]	3084	1			T3	168		T18	5		T117	1
valid_sources[0x6f]	3252	1			T3	182		T97	3		T99	3
valid_sources[0x70]	3486	1			T3	144		T6	12		T96	1
valid_sources[0x71]	3030	1			T3	179		T19	2		T12	1
valid_sources[0x72]	3702	1			T3	160		T5	1		T11	4
valid_sources[0x73]	2904	1			T3	200		T11	1		T117	1
valid_sources[0x74]	3767	1			T3	154		T19	1		T117	1
valid_sources[0x75]	3461	1			T3	176		T9	17		T16	36
valid_sources[0x76]	3589	1			T3	213		T5	1		T20	1
valid_sources[0x77]	3074	1			T3	156		T11	2		T96	1
valid_sources[0x78]	3369	1			T3	211		T11	2		T95	5
valid_sources[0x79]	3015	1			T3	203		T5	1		T11	1
valid_sources[0x7a]	3532	1			T3	195		T117	1		T97	1
valid_sources[0x7b]	3109	1			T3	146		T5	1		T11	1
valid_sources[0x7c]	3407	1			T3	153		T12	2		T117	2
valid_sources[0x7d]	3683	1			T3	221		T5	2		T11	1
valid_sources[0x7e]	3675	1			T3	162		T69	3		T117	1
valid_sources[0x7f]	3429	1			T3	191		T5	4		T117	2
valid_sources[0x80]	3667	1			T3	158		T11	2		T19	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

208419

1

T3

10252

T5

17

T6

27

values[0x0]

all_enables

biggest_size

308192

1

T3

15582

T13

85787

T14

90490

values[0x1]

all_enables

biggest_size

307939

1

T3

15472

T13

85937

T14

90384

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	66541	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

656244

1

T1

18

T3

32829

T5

39

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	183309	1			T1	37		T3	9126		T4	10
values[0x0]	249922	1			T3	12517		T10	3		T24	2
values[0x1]	289554	1			T3	14569		T10	4		T24	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	31196	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

691589

1

T1

23

T3

34733

T4

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2309	1			T3	135		T5	4		T119	1
valid_sources[0x01]	3494	1			T3	121		T122	1		T23	1
valid_sources[0x02]	2534	1			T3	123		T9	2		T71	1
valid_sources[0x03]	2095	1			T3	156		T32	1		T101	1
valid_sources[0x04]	2408	1			T3	158		T9	1		T16	1
valid_sources[0x05]	3604	1			T3	156		T30	1		T70	1
valid_sources[0x06]	3245	1			T3	125		T119	1		T123	10
valid_sources[0x07]	2379	1			T3	110		T30	1		T117	4
valid_sources[0x08]	2648	1			T3	121		T21	1		T117	3
valid_sources[0x09]	3015	1			T3	143		T121	1		T26	1
valid_sources[0x0a]	2987	1			T3	168		T5	1		T21	1
valid_sources[0x0b]	2557	1			T3	143		T5	1		T74	2
valid_sources[0x0c]	3259	1			T3	124		T124	2		T116	1
valid_sources[0x0d]	2614	1			T3	178		T125	1		T31	1
valid_sources[0x0e]	3238	1			T3	177		T30	1		T119	1
valid_sources[0x0f]	3201	1			T3	132		T16	1		T19	5
valid_sources[0x10]	2241	1			T3	134		T9	5		T71	5
valid_sources[0x11]	3470	1			T3	177		T8	1		T21	2
valid_sources[0x12]	2853	1			T3	172		T16	1		T124	1
valid_sources[0x13]	3401	1			T3	149		T124	1		T126	4
valid_sources[0x14]	2890	1			T3	136		T16	1		T72	1
valid_sources[0x15]	2759	1			T3	120		T30	1		T119	2
valid_sources[0x16]	2899	1			T3	194		T5	2		T70	1
valid_sources[0x17]	2570	1			T3	149		T5	1		T125	1
valid_sources[0x18]	3210	1			T3	138		T95	5		T127	1
valid_sources[0x19]	3617	1			T3	137		T95	8		T128	1
valid_sources[0x1a]	3844	1			T3	92		T57	1		T129	1
valid_sources[0x1b]	2877	1			T3	114		T69	2		T21	1
valid_sources[0x1c]	2750	1			T1	1		T3	99		T30	1
valid_sources[0x1d]	2987	1			T3	144		T5	1		T130	1
valid_sources[0x1e]	3048	1			T3	135		T30	1		T71	9
valid_sources[0x1f]	3052	1			T3	178		T30	2		T124	1
valid_sources[0x20]	1953	1			T1	1		T3	181		T5	1
valid_sources[0x21]	2971	1			T3	138		T73	3		T74	1
valid_sources[0x22]	3532	1			T1	3		T3	136		T70	2
valid_sources[0x23]	2185	1			T3	83		T69	6		T31	1
valid_sources[0x24]	3552	1			T3	123		T12	1		T95	2
valid_sources[0x25]	2532	1			T3	77		T74	1		T131	1
valid_sources[0x26]	2910	1			T3	125		T15	1		T31	1
valid_sources[0x27]	3153	1			T3	113		T124	1		T132	2
valid_sources[0x28]	3321	1			T3	142		T133	2		T134	1
valid_sources[0x29]	2872	1			T3	185		T119	1		T101	1
valid_sources[0x2a]	3149	1			T3	108		T5	1		T70	1
valid_sources[0x2b]	2529	1			T3	157		T121	2		T95	2
valid_sources[0x2c]	2669	1			T3	139		T124	1		T131	1
valid_sources[0x2d]	2286	1			T1	1		T3	158		T21	1
valid_sources[0x2e]	3617	1			T3	178		T71	2		T101	1
valid_sources[0x2f]	2350	1			T3	172		T30	1		T119	1
valid_sources[0x30]	2673	1			T1	2		T3	137		T16	1
valid_sources[0x31]	2169	1			T3	111		T21	1		T30	1
valid_sources[0x32]	3219	1			T3	170		T5	1		T54	1
valid_sources[0x33]	2313	1			T3	169		T12	3		T117	3
valid_sources[0x34]	2833	1			T1	2		T3	176		T18	96
valid_sources[0x35]	2476	1			T3	145		T95	1		T117	7
valid_sources[0x36]	2272	1			T3	141		T69	3		T30	1
valid_sources[0x37]	2929	1			T1	2		T3	121		T25	9
valid_sources[0x38]	3030	1			T3	108		T12	1		T95	2
valid_sources[0x39]	3270	1			T3	99		T5	1		T116	2
valid_sources[0x3a]	2949	1			T3	129		T95	1		T54	2
valid_sources[0x3b]	3035	1			T3	176		T5	1		T58	4
valid_sources[0x3c]	3550	1			T3	155		T122	4		T130	1
valid_sources[0x3d]	3247	1			T3	145		T16	1		T120	2
valid_sources[0x3e]	2928	1			T1	1		T3	159		T117	2
valid_sources[0x3f]	2533	1			T3	115		T4	10		T95	3
valid_sources[0x40]	3209	1			T3	146		T117	1		T119	1
valid_sources[0x41]	2359	1			T3	98		T5	1		T101	1
valid_sources[0x42]	2999	1			T3	126		T12	1		T131	1
valid_sources[0x43]	2612	1			T3	96		T31	2		T38	1
valid_sources[0x44]	3047	1			T3	158		T5	4		T16	1
valid_sources[0x45]	2906	1			T3	186		T117	2		T135	1
valid_sources[0x46]	2630	1			T3	124		T12	1		T117	1
valid_sources[0x47]	3375	1			T3	197		T117	1		T120	4
valid_sources[0x48]	2792	1			T3	187		T119	1		T73	1
valid_sources[0x49]	3356	1			T3	135		T101	1		T74	2
valid_sources[0x4a]	2615	1			T3	114		T15	3		T95	1
valid_sources[0x4b]	2665	1			T3	164		T15	7		T136	1
valid_sources[0x4c]	3046	1			T3	174		T21	1		T119	1
valid_sources[0x4d]	2944	1			T3	169		T15	3		T19	4
valid_sources[0x4e]	1899	1			T3	115		T12	1		T70	2
valid_sources[0x4f]	2937	1			T3	118		T73	4		T137	32
valid_sources[0x50]	2731	1			T3	217		T69	3		T71	1
valid_sources[0x51]	2759	1			T3	150		T15	2		T69	1
valid_sources[0x52]	3176	1			T3	164		T121	3		T124	1
valid_sources[0x53]	3077	1			T3	94		T121	2		T119	2
valid_sources[0x54]	2824	1			T3	137		T5	1		T30	2
valid_sources[0x55]	2812	1			T3	128		T19	11		T95	2
valid_sources[0x56]	2566	1			T3	134		T5	3		T9	4
valid_sources[0x57]	2461	1			T3	151		T30	1		T124	2
valid_sources[0x58]	2453	1			T3	136		T117	2		T101	1
valid_sources[0x59]	3264	1			T3	138		T119	1		T32	3
valid_sources[0x5a]	3025	1			T3	166		T21	1		T95	2
valid_sources[0x5b]	2990	1			T3	122		T16	1		T124	1
valid_sources[0x5c]	3007	1			T3	142		T70	1		T31	1
valid_sources[0x5d]	2395	1			T3	140		T16	1		T117	11
valid_sources[0x5e]	2397	1			T3	149		T24	1		T72	1
valid_sources[0x5f]	2362	1			T3	138		T12	1		T119	1
valid_sources[0x60]	2666	1			T1	1		T3	114		T119	1
valid_sources[0x61]	2761	1			T3	170		T16	1		T74	1
valid_sources[0x62]	2642	1			T3	132		T12	8		T74	2
valid_sources[0x63]	3070	1			T1	1		T3	133		T21	1
valid_sources[0x64]	3178	1			T3	162		T5	2		T21	1
valid_sources[0x65]	2272	1			T3	131		T13	354		T14	798
valid_sources[0x66]	2526	1			T1	2		T3	147		T95	3
valid_sources[0x67]	3050	1			T3	183		T138	1		T139	1
valid_sources[0x68]	2870	1			T3	140		T119	1		T140	1
valid_sources[0x69]	2785	1			T3	131		T21	1		T70	1
valid_sources[0x6a]	2986	1			T3	176		T119	1		T135	1
valid_sources[0x6b]	2541	1			T3	141		T117	1		T55	2
valid_sources[0x6c]	3079	1			T3	97		T69	1		T31	3
valid_sources[0x6d]	2544	1			T3	134		T54	1		T119	1
valid_sources[0x6e]	2923	1			T1	2		T3	127		T12	2
valid_sources[0x6f]	2809	1			T3	132		T125	1		T140	1
valid_sources[0x70]	2546	1			T3	172		T124	1		T126	1
valid_sources[0x71]	2643	1			T3	125		T21	1		T101	1
valid_sources[0x72]	3326	1			T3	141		T5	1		T15	1
valid_sources[0x73]	2838	1			T3	133		T5	2		T141	1
valid_sources[0x74]	2494	1			T3	154		T24	2		T124	1
valid_sources[0x75]	2843	1			T3	117		T140	1		T132	1
valid_sources[0x76]	2570	1			T3	152		T125	1		T142	3
valid_sources[0x77]	2206	1			T3	139		T5	1		T15	1
valid_sources[0x78]	2628	1			T3	101		T5	1		T69	1
valid_sources[0x79]	3160	1			T3	165		T5	2		T121	2
valid_sources[0x7a]	3121	1			T3	134		T121	1		T143	2
valid_sources[0x7b]	2665	1			T3	146		T5	1		T73	6
valid_sources[0x7c]	2552	1			T3	165		T5	1		T30	1
valid_sources[0x7d]	2095	1			T3	147		T119	3		T144	1
valid_sources[0x7e]	2564	1			T3	86		T21	1		T95	1
valid_sources[0x7f]	2439	1			T3	170		T124	1		T145	2
valid_sources[0x80]	2145	1			T3	138		T16	1		T74	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

166010

1

T1

18

T3

8431

T5

39

values[0x0]

all_enables

biggest_size

244696

1

T3

12285

T10

1

T25

2

values[0x1]

all_enables

biggest_size

245538

1

T3

12113

T10

1

T25

1