Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1516585

1

T3

78650

T5

137

T6

282

full_word

962342

1

T3

48420

T5

17

T6

27

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2478607	1			T3	127070		T5	154		T6	309
auto[TlIntgErrCmd]	94	1			T48	3		T49	10		T50	2
auto[TlIntgErrData]	111	1			T48	9		T49	5		T50	2
auto[TlIntgErrBoth]	115	1			T48	8		T49	5		T50	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

405362

1

T3

20228

T5

154

T6

309

auto[1]

2073565

1

T3

106842

T13

572305

T14

615878

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	176782	1			T3	8825		T5	137		T6	282
auto[TlIntgErrNone]	partial	auto[1]	1339505	1			T3	69825		T13	368157		T14	399887
auto[TlIntgErrNone]	full_word	auto[0]	228420	1			T3	11403		T5	17		T6	27
auto[TlIntgErrNone]	full_word	auto[1]	733900	1			T3	37017		T13	204148		T14	215991
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T48	2		T49	6		T50	2
auto[TlIntgErrCmd]	partial	auto[1]	42	1			T48	1		T49	4		T102	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T107	1		T108	1		T109	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T102	1		T107	1		T110	2
auto[TlIntgErrData]	partial	auto[0]	56	1			T48	2		T49	2		T102	3
auto[TlIntgErrData]	partial	auto[1]	45	1			T48	5		T49	3		T50	1
auto[TlIntgErrData]	full_word	auto[0]	8	1			T48	2		T107	3		T111	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T50	1		T105	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T48	5		T49	1		T50	3
auto[TlIntgErrBoth]	partial	auto[1]	64	1			T48	3		T49	4		T50	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T112	1		T109	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T106	1		T113	1		T114	1