Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	49612	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

951899

1

T1

23

T3

9

T4

33

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	271120	1			T1	269		T3	109		T4	389
values[0x0]	358631	1			T5	116061		T13	53924		T14	36974
values[0x1]	371760	1			T5	120454		T13	55844		T14	38133

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	24812	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

976699

1

T1

158

T3

72

T4

246

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3878	1			T3	1		T5	1174		T10	1
valid_sources[0x01]	3579	1			T3	1		T5	1008		T18	1
valid_sources[0x02]	3899	1			T1	1		T5	1204		T9	1
valid_sources[0x03]	3837	1			T1	1		T3	1		T5	1237
valid_sources[0x04]	4039	1			T3	1		T5	1279		T18	2
valid_sources[0x05]	3890	1			T5	1272		T18	1		T21	1
valid_sources[0x06]	3932	1			T3	1		T4	3		T5	1115
valid_sources[0x07]	4176	1			T5	1339		T18	1		T21	1
valid_sources[0x08]	4030	1			T1	1		T5	1261		T9	2
valid_sources[0x09]	4076	1			T3	1		T5	1475		T18	2
valid_sources[0x0a]	4127	1			T1	2		T3	1		T5	1395
valid_sources[0x0b]	4002	1			T1	1		T3	1		T5	1205
valid_sources[0x0c]	4222	1			T1	2		T5	1412		T18	2
valid_sources[0x0d]	4179	1			T4	11		T5	1373		T12	1
valid_sources[0x0e]	3935	1			T1	1		T5	1352		T21	1
valid_sources[0x0f]	3961	1			T1	2		T4	3		T5	1303
valid_sources[0x10]	4131	1			T1	2		T3	1		T5	1347
valid_sources[0x11]	3708	1			T3	1		T5	1097		T9	1
valid_sources[0x12]	3989	1			T1	1		T3	2		T4	16
valid_sources[0x13]	3693	1			T1	3		T5	1000		T10	1
valid_sources[0x14]	3878	1			T3	1		T5	1208		T10	1
valid_sources[0x15]	3945	1			T4	7		T5	1168		T21	4
valid_sources[0x16]	3991	1			T5	1261		T9	1		T18	1
valid_sources[0x17]	3978	1			T1	4		T4	7		T5	1205
valid_sources[0x18]	4086	1			T1	2		T4	3		T5	1309
valid_sources[0x19]	3947	1			T1	1		T3	2		T5	1304
valid_sources[0x1a]	3892	1			T3	1		T5	1190		T9	1
valid_sources[0x1b]	4050	1			T1	1		T5	1378		T12	2
valid_sources[0x1c]	3803	1			T1	2		T4	14		T5	1178
valid_sources[0x1d]	3668	1			T1	2		T5	954		T21	1
valid_sources[0x1e]	3847	1			T5	1257		T12	1		T31	4
valid_sources[0x1f]	3988	1			T1	1		T5	1248		T10	1
valid_sources[0x20]	3851	1			T1	2		T3	1		T5	1133
valid_sources[0x21]	3844	1			T1	3		T5	1165		T9	3
valid_sources[0x22]	3904	1			T1	1		T3	2		T5	1102
valid_sources[0x23]	3812	1			T1	1		T4	1		T5	1157
valid_sources[0x24]	4021	1			T1	2		T4	2		T5	1341
valid_sources[0x25]	3992	1			T1	1		T3	1		T4	2
valid_sources[0x26]	3773	1			T4	6		T5	1182		T21	1
valid_sources[0x27]	4018	1			T1	2		T5	1311		T9	2
valid_sources[0x28]	3941	1			T5	1163		T10	1		T18	3
valid_sources[0x29]	3941	1			T1	1		T5	1343		T9	4
valid_sources[0x2a]	3681	1			T5	1141		T9	1		T10	1
valid_sources[0x2b]	3949	1			T1	1		T5	1296		T18	2
valid_sources[0x2c]	3897	1			T1	1		T3	1		T5	1352
valid_sources[0x2d]	3777	1			T1	1		T5	1202		T19	4
valid_sources[0x2e]	4073	1			T1	3		T4	9		T5	1358
valid_sources[0x2f]	3829	1			T1	1		T5	1144		T10	1
valid_sources[0x30]	3870	1			T1	1		T5	1186		T18	1
valid_sources[0x31]	4076	1			T1	2		T5	1393		T18	2
valid_sources[0x32]	4049	1			T3	1		T4	2		T5	1361
valid_sources[0x33]	3795	1			T1	2		T3	1		T5	1175
valid_sources[0x34]	3979	1			T1	1		T5	1266		T10	1
valid_sources[0x35]	3735	1			T5	1082		T18	2		T13	615
valid_sources[0x36]	3782	1			T5	1116		T9	2		T21	1
valid_sources[0x37]	3877	1			T1	1		T3	1		T5	1212
valid_sources[0x38]	4184	1			T1	2		T3	1		T5	1274
valid_sources[0x39]	3791	1			T3	1		T5	1047		T18	1
valid_sources[0x3a]	3711	1			T1	1		T3	1		T5	1280
valid_sources[0x3b]	4082	1			T1	1		T3	2		T5	1368
valid_sources[0x3c]	3887	1			T1	2		T5	1224		T9	2
valid_sources[0x3d]	3819	1			T1	1		T5	1152		T18	1
valid_sources[0x3e]	3740	1			T1	1		T3	1		T5	1096
valid_sources[0x3f]	3858	1			T1	2		T5	1070		T18	1
valid_sources[0x40]	4067	1			T3	1		T4	3		T5	1359
valid_sources[0x41]	3605	1			T1	2		T5	1008		T18	2
valid_sources[0x42]	3883	1			T3	2		T5	1158		T18	1
valid_sources[0x43]	3793	1			T5	1174		T18	2		T21	1
valid_sources[0x44]	3769	1			T1	1		T5	1172		T10	1
valid_sources[0x45]	3851	1			T5	1079		T30	6		T32	6
valid_sources[0x46]	3944	1			T1	2		T5	1247		T21	3
valid_sources[0x47]	3845	1			T1	1		T5	1248		T21	2
valid_sources[0x48]	3730	1			T4	4		T5	1075		T10	2
valid_sources[0x49]	3861	1			T5	1251		T10	2		T18	2
valid_sources[0x4a]	3927	1			T1	4		T3	1		T4	7
valid_sources[0x4b]	4058	1			T1	2		T4	6		T5	1329
valid_sources[0x4c]	3747	1			T5	1088		T9	1		T10	1
valid_sources[0x4d]	3888	1			T1	1		T5	1310		T9	1
valid_sources[0x4e]	3811	1			T1	1		T3	1		T4	7
valid_sources[0x4f]	3963	1			T1	2		T5	1233		T10	1
valid_sources[0x50]	3911	1			T5	1357		T18	1		T32	4
valid_sources[0x51]	4056	1			T5	1379		T18	2		T66	1
valid_sources[0x52]	3864	1			T1	1		T3	1		T5	1188
valid_sources[0x53]	3815	1			T1	2		T3	1		T5	1280
valid_sources[0x54]	3961	1			T1	1		T5	1273		T66	2
valid_sources[0x55]	4026	1			T3	2		T5	1324		T9	1
valid_sources[0x56]	3890	1			T3	1		T5	1288		T10	2
valid_sources[0x57]	4073	1			T5	1379		T18	1		T21	1
valid_sources[0x58]	4047	1			T1	1		T3	1		T5	1221
valid_sources[0x59]	4012	1			T3	1		T5	1154		T18	3
valid_sources[0x5a]	3940	1			T1	1		T4	3		T5	1355
valid_sources[0x5b]	3702	1			T5	1106		T66	2		T32	1
valid_sources[0x5c]	3717	1			T5	1078		T19	5		T21	1
valid_sources[0x5d]	3853	1			T1	1		T3	1		T5	1264
valid_sources[0x5e]	3974	1			T1	3		T3	1		T5	1354
valid_sources[0x5f]	3853	1			T1	2		T3	2		T5	1163
valid_sources[0x60]	3938	1			T5	1240		T18	3		T12	4
valid_sources[0x61]	4105	1			T3	1		T5	1222		T18	1
valid_sources[0x62]	3877	1			T5	1119		T66	1		T13	615
valid_sources[0x63]	4003	1			T1	1		T4	4		T5	1271
valid_sources[0x64]	3873	1			T1	1		T5	1197		T13	620
valid_sources[0x65]	3862	1			T4	2		T5	1183		T10	2
valid_sources[0x66]	3984	1			T5	1273		T9	1		T66	2
valid_sources[0x67]	3742	1			T4	8		T5	1150		T9	1
valid_sources[0x68]	4014	1			T1	1		T5	1232		T9	2
valid_sources[0x69]	3897	1			T1	2		T5	1223		T9	2
valid_sources[0x6a]	3952	1			T1	2		T3	1		T5	1263
valid_sources[0x6b]	4050	1			T1	1		T5	1303		T13	547
valid_sources[0x6c]	3812	1			T1	1		T3	1		T5	1263
valid_sources[0x6d]	4029	1			T5	1307		T9	1		T18	2
valid_sources[0x6e]	3842	1			T1	2		T5	1191		T10	1
valid_sources[0x6f]	3937	1			T1	3		T4	8		T5	1279
valid_sources[0x70]	3913	1			T3	1		T5	1168		T17	4
valid_sources[0x71]	3862	1			T1	2		T3	1		T5	1197
valid_sources[0x72]	4042	1			T1	1		T3	2		T5	1405
valid_sources[0x73]	4024	1			T1	3		T5	1304		T9	1
valid_sources[0x74]	3621	1			T1	1		T3	1		T5	1033
valid_sources[0x75]	4005	1			T5	1275		T18	1		T21	1
valid_sources[0x76]	4056	1			T5	1323		T104	1		T66	1
valid_sources[0x77]	3842	1			T1	1		T3	2		T4	4
valid_sources[0x78]	3986	1			T1	1		T5	1157		T9	1
valid_sources[0x79]	3978	1			T4	4		T5	1369		T104	4
valid_sources[0x7a]	3772	1			T1	1		T5	1058		T32	4
valid_sources[0x7b]	4060	1			T5	1273		T9	1		T18	1
valid_sources[0x7c]	3714	1			T3	1		T5	1191		T9	1
valid_sources[0x7d]	3893	1			T1	3		T5	1299		T19	16
valid_sources[0x7e]	4103	1			T1	3		T5	1375		T9	1
valid_sources[0x7f]	3780	1			T1	1		T5	1046		T32	1
valid_sources[0x80]	3789	1			T1	2		T4	7		T5	1144

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

240939

1

T1

23

T3

9

T4

33

values[0x0]

all_enables

biggest_size

355564

1

T5

115091

T13

53477

T14

36629

values[0x1]

all_enables

biggest_size

355396

1

T5

115187

T13

53433

T14

36445

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	76875	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

734013

1

T3

37

T5

231105

T9

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	205950	1			T2	1		T3	64		T5	62567
values[0x0]	279695	1			T5	88026		T7	2		T8	8
values[0x1]	325243	1			T5	102745		T7	5		T8	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35695	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

775193

1

T3

42

T5

243786

T7

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3273	1			T5	1008		T13	434		T78	6
valid_sources[0x01]	3292	1			T5	996		T13	445		T14	331
valid_sources[0x02]	3020	1			T5	991		T13	466		T41	1
valid_sources[0x03]	3495	1			T5	1029		T13	441		T14	303
valid_sources[0x04]	3599	1			T5	1075		T13	440		T14	345
valid_sources[0x05]	2849	1			T5	1004		T13	473		T77	1
valid_sources[0x06]	3361	1			T5	919		T13	439		T40	1
valid_sources[0x07]	2831	1			T5	979		T30	1		T25	1
valid_sources[0x08]	2916	1			T5	894		T20	1		T44	1
valid_sources[0x09]	2787	1			T5	1011		T25	2		T13	481
valid_sources[0x0a]	3040	1			T5	1002		T19	6		T104	1
valid_sources[0x0b]	3042	1			T5	941		T13	405		T14	285
valid_sources[0x0c]	3217	1			T5	989		T22	1		T13	450
valid_sources[0x0d]	2909	1			T5	989		T19	1		T121	1
valid_sources[0x0e]	3061	1			T5	954		T13	508		T14	299
valid_sources[0x0f]	3055	1			T5	1026		T7	1		T25	1
valid_sources[0x10]	3318	1			T3	3		T5	1063		T9	1
valid_sources[0x11]	2843	1			T5	964		T104	2		T13	474
valid_sources[0x12]	3274	1			T5	1016		T9	1		T13	463
valid_sources[0x13]	3966	1			T5	947		T104	2		T13	465
valid_sources[0x14]	3292	1			T5	1015		T52	6		T13	459
valid_sources[0x15]	3102	1			T5	1046		T13	441		T79	1
valid_sources[0x16]	2754	1			T5	978		T104	1		T13	500
valid_sources[0x17]	3118	1			T5	979		T24	20		T13	440
valid_sources[0x18]	3001	1			T5	1039		T20	1		T30	2
valid_sources[0x19]	3367	1			T5	924		T13	483		T122	1
valid_sources[0x1a]	3093	1			T5	941		T13	479		T14	356
valid_sources[0x1b]	2875	1			T5	1004		T13	489		T77	1
valid_sources[0x1c]	3277	1			T5	1016		T13	491		T14	320
valid_sources[0x1d]	2970	1			T5	959		T22	2		T13	467
valid_sources[0x1e]	3092	1			T5	1017		T13	415		T122	2
valid_sources[0x1f]	2889	1			T5	1061		T9	2		T13	462
valid_sources[0x20]	3041	1			T5	949		T22	3		T13	515
valid_sources[0x21]	2996	1			T5	1028		T27	1		T23	1
valid_sources[0x22]	3604	1			T5	1040		T67	1		T30	6
valid_sources[0x23]	3271	1			T5	1004		T13	480		T79	2
valid_sources[0x24]	2848	1			T3	3		T5	957		T13	452
valid_sources[0x25]	2862	1			T5	984		T13	401		T79	1
valid_sources[0x26]	3213	1			T5	972		T13	419		T14	307
valid_sources[0x27]	3126	1			T5	1024		T13	458		T80	1
valid_sources[0x28]	3361	1			T5	1055		T20	1		T13	489
valid_sources[0x29]	2899	1			T5	1003		T9	1		T13	487
valid_sources[0x2a]	3224	1			T5	974		T13	466		T122	1
valid_sources[0x2b]	3305	1			T5	1018		T19	6		T13	457
valid_sources[0x2c]	2860	1			T5	933		T13	430		T122	1
valid_sources[0x2d]	3042	1			T3	5		T5	945		T25	1
valid_sources[0x2e]	3091	1			T5	992		T30	2		T13	539
valid_sources[0x2f]	2891	1			T5	903		T22	1		T13	437
valid_sources[0x30]	3004	1			T5	962		T13	515		T14	374
valid_sources[0x31]	3195	1			T5	1031		T104	4		T13	426
valid_sources[0x32]	3289	1			T3	2		T5	1008		T30	3
valid_sources[0x33]	2827	1			T5	882		T13	439		T77	1
valid_sources[0x34]	3662	1			T5	1043		T13	482		T14	261
valid_sources[0x35]	3482	1			T5	968		T19	2		T22	3
valid_sources[0x36]	2945	1			T5	1018		T30	2		T13	465
valid_sources[0x37]	3442	1			T5	1073		T9	1		T13	484
valid_sources[0x38]	2691	1			T5	896		T13	404		T122	1
valid_sources[0x39]	2963	1			T5	990		T13	417		T40	1
valid_sources[0x3a]	2894	1			T5	954		T67	1		T13	472
valid_sources[0x3b]	3748	1			T5	986		T22	1		T13	439
valid_sources[0x3c]	3161	1			T5	1005		T13	486		T122	3
valid_sources[0x3d]	3171	1			T5	1036		T9	1		T22	1
valid_sources[0x3e]	3633	1			T5	1037		T13	434		T122	2
valid_sources[0x3f]	2915	1			T5	969		T63	8		T13	423
valid_sources[0x40]	2990	1			T5	984		T13	429		T14	309
valid_sources[0x41]	2897	1			T3	1		T5	993		T9	1
valid_sources[0x42]	2958	1			T5	971		T30	13		T13	474
valid_sources[0x43]	2863	1			T2	1		T5	987		T22	3
valid_sources[0x44]	2952	1			T5	952		T13	486		T14	349
valid_sources[0x45]	3662	1			T5	1038		T13	540		T122	1
valid_sources[0x46]	2944	1			T5	1013		T22	2		T13	447
valid_sources[0x47]	2957	1			T5	1029		T19	1		T13	490
valid_sources[0x48]	3365	1			T5	943		T9	1		T13	435
valid_sources[0x49]	3198	1			T5	1023		T9	1		T10	5
valid_sources[0x4a]	3730	1			T5	981		T25	2		T13	505
valid_sources[0x4b]	3151	1			T5	1006		T17	32		T31	4
valid_sources[0x4c]	3554	1			T3	3		T5	985		T20	1
valid_sources[0x4d]	3167	1			T5	930		T9	2		T37	10
valid_sources[0x4e]	3193	1			T5	1001		T67	1		T30	3
valid_sources[0x4f]	3469	1			T5	933		T67	2		T13	404
valid_sources[0x50]	2863	1			T5	968		T67	8		T13	510
valid_sources[0x51]	2995	1			T5	986		T19	3		T30	1
valid_sources[0x52]	3016	1			T5	1044		T7	3		T22	1
valid_sources[0x53]	3168	1			T3	1		T5	1008		T104	1
valid_sources[0x54]	2944	1			T5	985		T45	1		T25	1
valid_sources[0x55]	2952	1			T5	997		T19	11		T13	428
valid_sources[0x56]	3248	1			T5	1012		T9	1		T13	443
valid_sources[0x57]	4035	1			T5	976		T13	449		T36	28
valid_sources[0x58]	2844	1			T5	1016		T19	1		T13	473
valid_sources[0x59]	3332	1			T3	2		T5	1032		T19	3
valid_sources[0x5a]	3033	1			T5	1050		T13	404		T14	300
valid_sources[0x5b]	3011	1			T5	970		T13	495		T14	378
valid_sources[0x5c]	2804	1			T5	953		T22	1		T13	500
valid_sources[0x5d]	3062	1			T5	984		T22	1		T104	1
valid_sources[0x5e]	3210	1			T5	978		T20	1		T30	3
valid_sources[0x5f]	3194	1			T5	950		T13	473		T34	1
valid_sources[0x60]	3350	1			T5	1080		T30	1		T13	494
valid_sources[0x61]	3784	1			T5	993		T13	533		T122	1
valid_sources[0x62]	3387	1			T5	1002		T13	508		T14	303
valid_sources[0x63]	3089	1			T5	962		T13	445		T14	347
valid_sources[0x64]	2773	1			T3	1		T5	1030		T13	413
valid_sources[0x65]	2989	1			T5	992		T13	482		T14	314
valid_sources[0x66]	3255	1			T5	953		T19	3		T23	4
valid_sources[0x67]	2816	1			T5	954		T13	427		T79	1
valid_sources[0x68]	3324	1			T3	8		T5	1042		T13	500
valid_sources[0x69]	3077	1			T5	975		T13	426		T14	349
valid_sources[0x6a]	3723	1			T5	995		T13	443		T122	1
valid_sources[0x6b]	3196	1			T5	982		T11	1		T13	468
valid_sources[0x6c]	3430	1			T5	968		T13	499		T14	261
valid_sources[0x6d]	2944	1			T5	892		T31	1		T13	433
valid_sources[0x6e]	3226	1			T5	1025		T27	1		T104	1
valid_sources[0x6f]	3574	1			T5	968		T64	1		T13	479
valid_sources[0x70]	3380	1			T5	1019		T13	428		T79	1
valid_sources[0x71]	3306	1			T5	1064		T104	3		T13	494
valid_sources[0x72]	2702	1			T3	4		T5	977		T13	409
valid_sources[0x73]	3890	1			T5	1015		T13	516		T122	2
valid_sources[0x74]	3293	1			T5	996		T42	10		T13	452
valid_sources[0x75]	3142	1			T5	980		T23	1		T13	465
valid_sources[0x76]	2982	1			T5	1047		T30	7		T13	454
valid_sources[0x77]	2739	1			T5	977		T19	4		T13	405
valid_sources[0x78]	2840	1			T5	1021		T6	1		T67	1
valid_sources[0x79]	3918	1			T3	3		T5	1025		T13	492
valid_sources[0x7a]	3293	1			T5	1016		T22	1		T13	454
valid_sources[0x7b]	3236	1			T5	947		T8	11		T22	1
valid_sources[0x7c]	2747	1			T5	932		T10	2		T13	457
valid_sources[0x7d]	3919	1			T5	1059		T13	472		T79	1
valid_sources[0x7e]	3828	1			T5	977		T9	1		T13	453
valid_sources[0x7f]	3098	1			T5	992		T13	448		T34	2
valid_sources[0x80]	3005	1			T5	1005		T104	2		T23	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

186747

1

T3

37

T5

58410

T9

13

values[0x0]

all_enables

biggest_size

273469

1

T5

86242

T27

5

T44

1

values[0x1]

all_enables

biggest_size

273797

1

T5

86453

T37

1

T44

1