Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1751671

1

T1

246

T3

100

T4

356

full_word

1110329

1

T1

23

T3

9

T4

33

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2861710	1			T1	269		T3	109		T4	389
auto[TlIntgErrCmd]	93	1			T57	4		T58	3		T59	8
auto[TlIntgErrData]	96	1			T57	2		T58	2		T59	8
auto[TlIntgErrBoth]	101	1			T57	4		T58	5		T59	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

463456

1

T1

269

T3

109

T4

389

auto[1]

2398544

1

T5

778951

T13

364076

T14

249056

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	199472	1			T1	246		T3	100		T4	356
auto[TlIntgErrNone]	partial	auto[1]	1551933	1			T5	504554		T13	236582		T14	161808
auto[TlIntgErrNone]	full_word	auto[0]	263867	1			T1	23		T3	9		T4	33
auto[TlIntgErrNone]	full_word	auto[1]	846438	1			T5	274397		T13	127494		T14	87248
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T57	2		T58	2		T59	1
auto[TlIntgErrCmd]	partial	auto[1]	49	1			T57	1		T58	1		T59	7
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T57	1		T107	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T111	1		T115	1		T116	1
auto[TlIntgErrData]	partial	auto[0]	38	1			T57	2		T59	3		T108	2
auto[TlIntgErrData]	partial	auto[1]	49	1			T58	2		T59	4		T117	4
auto[TlIntgErrData]	full_word	auto[0]	2	1			T59	1		T110	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	7	1			T111	1		T115	1		T113	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T57	1		T58	2		T59	1
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T57	3		T58	3		T59	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T118	2		T119	1		T116	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T111	1		T109	1		T119	1