Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1320161

1

T1

77

T3

52

T5

48

full_word

846876

1

T1

9

T3

3

T5

9

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2166727	1			T1	86		T3	55		T5	57
auto[TlIntgErrCmd]	108	1			T57	2		T58	5		T110	7
auto[TlIntgErrData]	105	1			T57	3		T58	8		T59	3
auto[TlIntgErrBoth]	97	1			T57	5		T58	7		T59	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

358936

1

T1

86

T3

55

T5

57

auto[1]

1808101

1

T7

309286

T12

85325

T13

352085

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	157061	1			T1	77		T3	52		T5	48
auto[TlIntgErrNone]	partial	auto[1]	1162811	1			T7	198899		T12	54097		T13	226318
auto[TlIntgErrNone]	full_word	auto[0]	201728	1			T1	9		T3	3		T5	9
auto[TlIntgErrNone]	full_word	auto[1]	645127	1			T7	110387		T12	31228		T13	125767
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T57	2		T58	2		T110	3
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T58	3		T110	3		T111	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T110	1		T117	1		T119	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T114	1		T120	1		T121	1
auto[TlIntgErrData]	partial	auto[0]	54	1			T57	1		T58	4		T59	2
auto[TlIntgErrData]	partial	auto[1]	44	1			T57	1		T58	2		T110	4
auto[TlIntgErrData]	full_word	auto[0]	3	1			T58	1		T59	1		T115	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T57	1		T58	1		T111	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T57	1		T58	3		T59	2
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T57	3		T58	4		T59	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T57	1		T59	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T112	2		T115	1		-	-