Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 41541 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 722285 1 T1 15 T2 8 T3 7



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 209942 1 T1 91 T2 69 T3 94
values[0x0] 272212 1 T14 19814 T15 27859 T16 23101
values[0x1] 281672 1 T14 20286 T15 28992 T16 23860



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 20588 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 743238 1 T1 60 T2 43 T3 57



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 3111 1 T3 1 T11 1 T39 1
valid_sources[0x01] 3082 1 T3 1 T11 1 T32 7
valid_sources[0x02] 2957 1 T2 4 T3 1 T17 1
valid_sources[0x03] 2962 1 T11 3 T19 3 T36 9
valid_sources[0x04] 2876 1 T1 2 T36 2 T38 1
valid_sources[0x05] 3026 1 T3 1 T11 2 T20 1
valid_sources[0x06] 2929 1 T17 1 T83 1 T85 4
valid_sources[0x07] 2944 1 T86 2 T126 3 T14 205
valid_sources[0x08] 2972 1 T11 2 T35 4 T38 1
valid_sources[0x09] 3175 1 T3 1 T11 2 T19 1
valid_sources[0x0a] 2940 1 T1 1 T3 2 T11 2
valid_sources[0x0b] 3049 1 T31 7 T38 1 T82 1
valid_sources[0x0c] 2888 1 T3 1 T17 1 T11 1
valid_sources[0x0d] 2976 1 T11 1 T19 1 T38 2
valid_sources[0x0e] 2943 1 T11 2 T31 5 T38 1
valid_sources[0x0f] 2958 1 T1 2 T11 1 T22 10
valid_sources[0x10] 3130 1 T1 6 T13 3 T35 1
valid_sources[0x11] 2878 1 T1 2 T21 19 T11 2
valid_sources[0x12] 2951 1 T2 2 T17 1 T11 1
valid_sources[0x13] 3049 1 T11 1 T13 3 T38 1
valid_sources[0x14] 2829 1 T35 2 T126 3 T14 226
valid_sources[0x15] 3061 1 T11 2 T13 1 T38 1
valid_sources[0x16] 3044 1 T11 2 T82 11 T127 1
valid_sources[0x17] 3073 1 T11 1 T19 5 T35 1
valid_sources[0x18] 2984 1 T3 1 T86 2 T126 2
valid_sources[0x19] 2910 1 T1 1 T3 1 T35 1
valid_sources[0x1a] 2975 1 T39 2 T128 12 T86 1
valid_sources[0x1b] 3193 1 T17 1 T11 2 T13 2
valid_sources[0x1c] 3243 1 T3 2 T38 3 T127 1
valid_sources[0x1d] 3018 1 T11 1 T42 1 T126 4
valid_sources[0x1e] 2928 1 T13 1 T127 3 T86 1
valid_sources[0x1f] 3055 1 T3 1 T11 1 T39 2
valid_sources[0x20] 3017 1 T3 2 T11 1 T13 3
valid_sources[0x21] 3057 1 T11 1 T84 4 T85 8
valid_sources[0x22] 3009 1 T13 1 T126 3 T14 217
valid_sources[0x23] 2924 1 T17 1 T11 2 T19 1
valid_sources[0x24] 2907 1 T1 1 T17 3 T24 1
valid_sources[0x25] 2966 1 T38 6 T39 2 T86 1
valid_sources[0x26] 2894 1 T19 1 T86 1 T14 182
valid_sources[0x27] 2910 1 T11 1 T38 2 T84 2
valid_sources[0x28] 2926 1 T3 1 T11 1 T38 1
valid_sources[0x29] 2955 1 T2 8 T3 1 T11 1
valid_sources[0x2a] 2975 1 T3 1 T17 3 T11 1
valid_sources[0x2b] 3029 1 T1 1 T17 1 T11 2
valid_sources[0x2c] 2974 1 T3 1 T21 72 T13 3
valid_sources[0x2d] 2969 1 T11 2 T13 1 T36 5
valid_sources[0x2e] 3023 1 T3 1 T11 2 T19 1
valid_sources[0x2f] 3007 1 T3 2 T31 2 T35 1
valid_sources[0x30] 2868 1 T1 2 T2 6 T13 9
valid_sources[0x31] 2796 1 T11 1 T22 4 T126 4
valid_sources[0x32] 3212 1 T2 2 T11 1 T38 1
valid_sources[0x33] 3086 1 T11 1 T20 1 T83 2
valid_sources[0x34] 2962 1 T17 1 T11 2 T127 1
valid_sources[0x35] 3262 1 T11 1 T22 4 T38 2
valid_sources[0x36] 3054 1 T11 2 T38 1 T44 1
valid_sources[0x37] 2970 1 T1 1 T11 3 T13 1
valid_sources[0x38] 2968 1 T17 2 T31 9 T36 1
valid_sources[0x39] 2989 1 T17 1 T11 1 T19 1
valid_sources[0x3a] 2971 1 T38 2 T128 88 T85 6
valid_sources[0x3b] 2950 1 T11 4 T13 1 T31 2
valid_sources[0x3c] 2928 1 T11 2 T19 1 T13 2
valid_sources[0x3d] 3026 1 T44 1 T85 1 T86 1
valid_sources[0x3e] 2871 1 T11 3 T13 2 T38 3
valid_sources[0x3f] 3030 1 T3 1 T11 1 T86 2
valid_sources[0x40] 3035 1 T1 4 T3 1 T11 2
valid_sources[0x41] 2990 1 T19 2 T38 2 T42 1
valid_sources[0x42] 3161 1 T3 1 T11 2 T86 2
valid_sources[0x43] 3056 1 T1 2 T11 3 T36 9
valid_sources[0x44] 2861 1 T11 2 T85 2 T86 1
valid_sources[0x45] 3065 1 T11 1 T19 2 T31 7
valid_sources[0x46] 2954 1 T2 4 T3 1 T17 1
valid_sources[0x47] 2932 1 T3 1 T31 8 T38 2
valid_sources[0x48] 2955 1 T11 1 T13 1 T36 3
valid_sources[0x49] 3067 1 T17 3 T13 2 T38 2
valid_sources[0x4a] 3046 1 T1 2 T3 1 T11 1
valid_sources[0x4b] 3232 1 T11 2 T13 3 T38 1
valid_sources[0x4c] 2966 1 T17 2 T11 1 T39 1
valid_sources[0x4d] 2823 1 T11 4 T35 1 T36 2
valid_sources[0x4e] 2913 1 T3 1 T17 1 T36 1
valid_sources[0x4f] 2916 1 T17 1 T11 3 T32 1
valid_sources[0x50] 3217 1 T1 2 T3 1 T12 61
valid_sources[0x51] 3008 1 T38 3 T39 1 T127 1
valid_sources[0x52] 3088 1 T3 1 T11 1 T19 1
valid_sources[0x53] 2960 1 T3 1 T11 1 T22 4
valid_sources[0x54] 3154 1 T11 2 T13 1 T35 1
valid_sources[0x55] 3061 1 T11 1 T38 2 T82 5
valid_sources[0x56] 3057 1 T11 1 T23 1 T32 3
valid_sources[0x57] 2922 1 T2 12 T21 37 T17 1
valid_sources[0x58] 2972 1 T11 1 T38 1 T14 223
valid_sources[0x59] 2946 1 T3 1 T11 1 T86 2
valid_sources[0x5a] 2910 1 T13 1 T38 1 T82 9
valid_sources[0x5b] 2955 1 T1 1 T2 2 T38 3
valid_sources[0x5c] 2863 1 T1 1 T11 1 T13 1
valid_sources[0x5d] 2937 1 T11 2 T36 6 T39 1
valid_sources[0x5e] 2915 1 T11 3 T36 1 T86 1
valid_sources[0x5f] 3079 1 T13 3 T127 1 T85 2
valid_sources[0x60] 2977 1 T39 1 T129 16 T127 1
valid_sources[0x61] 2998 1 T11 2 T36 5 T38 3
valid_sources[0x62] 3087 1 T19 2 T13 1 T38 2
valid_sources[0x63] 3092 1 T3 1 T19 1 T13 2
valid_sources[0x64] 3010 1 T17 1 T11 1 T36 6
valid_sources[0x65] 3118 1 T1 8 T2 3 T19 1
valid_sources[0x66] 2930 1 T39 2 T86 1 T126 1
valid_sources[0x67] 2883 1 T31 2 T38 4 T39 1
valid_sources[0x68] 2927 1 T38 1 T86 1 T14 214
valid_sources[0x69] 2926 1 T3 1 T86 1 T126 3
valid_sources[0x6a] 3020 1 T1 6 T3 1 T11 3
valid_sources[0x6b] 3139 1 T3 1 T11 2 T35 1
valid_sources[0x6c] 3063 1 T1 1 T3 2 T39 1
valid_sources[0x6d] 3096 1 T17 3 T13 3 T36 13
valid_sources[0x6e] 2949 1 T11 1 T19 1 T38 1
valid_sources[0x6f] 3042 1 T35 1 T36 11 T38 3
valid_sources[0x70] 2896 1 T1 1 T22 21 T13 2
valid_sources[0x71] 2942 1 T3 1 T24 2 T38 3
valid_sources[0x72] 2978 1 T3 2 T36 27 T14 212
valid_sources[0x73] 2940 1 T2 3 T11 1 T22 8
valid_sources[0x74] 2992 1 T3 1 T17 2 T13 7
valid_sources[0x75] 3024 1 T11 1 T32 12 T38 2
valid_sources[0x76] 2940 1 T11 1 T35 1 T85 8
valid_sources[0x77] 2820 1 T3 1 T13 2 T35 1
valid_sources[0x78] 2972 1 T1 1 T11 2 T13 7
valid_sources[0x79] 2759 1 T3 1 T11 1 T19 1
valid_sources[0x7a] 3037 1 T12 24 T13 6 T36 1
valid_sources[0x7b] 3017 1 T11 2 T13 3 T39 2
valid_sources[0x7c] 2895 1 T1 1 T3 1 T11 1
valid_sources[0x7d] 3122 1 T86 1 T126 5 T14 211
valid_sources[0x7e] 2935 1 T3 1 T11 2 T19 1
valid_sources[0x7f] 2857 1 T1 1 T17 1 T11 1
valid_sources[0x80] 2963 1 T17 1 T36 1 T38 6



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 183043 1 T1 15 T2 8 T3 7
values[0x0] all_enables biggest_size 269824 1 T14 19634 T15 27615 T16 22877
values[0x1] all_enables biggest_size 269418 1 T14 19350 T15 27734 T16 22779


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 58619 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 556327 1 T1 14 T2 16 T3 22



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 156775 1 T1 32 T2 32 T3 32
values[0x0] 212581 1 T7 3 T8 11 T10 1
values[0x1] 245590 1 T8 5 T10 1 T66 1



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 27758 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 587188 1 T1 16 T2 17 T3 27



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 2180 1 T44 1 T127 1 T130 1
valid_sources[0x01] 2767 1 T8 5 T83 1 T131 15
valid_sources[0x02] 2198 1 T83 1 T43 2 T85 1
valid_sources[0x03] 2134 1 T38 1 T127 1 T14 214
valid_sources[0x04] 2760 1 T2 1 T13 64 T14 180
valid_sources[0x05] 2691 1 T38 1 T85 2 T14 160
valid_sources[0x06] 2298 1 T64 1 T132 1 T14 181
valid_sources[0x07] 2565 1 T36 1 T38 1 T129 1
valid_sources[0x08] 2425 1 T35 32 T40 1 T14 183
valid_sources[0x09] 2104 1 T6 1 T24 3 T36 2
valid_sources[0x0a] 2202 1 T36 2 T84 1 T127 1
valid_sources[0x0b] 2001 1 T25 1 T14 177 T15 206
valid_sources[0x0c] 2434 1 T2 1 T36 4 T42 1
valid_sources[0x0d] 2168 1 T2 1 T38 2 T41 8
valid_sources[0x0e] 2053 1 T38 2 T67 1 T14 177
valid_sources[0x0f] 1804 1 T85 1 T130 1 T14 181
valid_sources[0x10] 2219 1 T17 1 T36 1 T83 2
valid_sources[0x11] 2872 1 T7 1 T38 1 T84 1
valid_sources[0x12] 1988 1 T2 1 T14 182 T15 161
valid_sources[0x13] 2458 1 T38 1 T40 1 T82 1
valid_sources[0x14] 2387 1 T17 2 T38 2 T44 1
valid_sources[0x15] 2671 1 T3 6 T14 197 T15 277
valid_sources[0x16] 1929 1 T82 1 T83 2 T14 182
valid_sources[0x17] 1996 1 T24 1 T38 3 T14 181
valid_sources[0x18] 2147 1 T25 1 T36 1 T84 1
valid_sources[0x19] 2524 1 T32 32 T36 1 T38 3
valid_sources[0x1a] 2225 1 T36 1 T85 1 T132 1
valid_sources[0x1b] 2609 1 T20 1 T44 1 T85 2
valid_sources[0x1c] 2153 1 T84 1 T14 194 T58 1
valid_sources[0x1d] 2211 1 T14 179 T15 259 T133 1
valid_sources[0x1e] 2255 1 T2 1 T36 1 T82 1
valid_sources[0x1f] 2809 1 T42 1 T14 176 T15 190
valid_sources[0x20] 2503 1 T14 185 T15 278 T134 1
valid_sources[0x21] 2291 1 T83 1 T130 1 T14 191
valid_sources[0x22] 2412 1 T3 2 T20 1 T36 1
valid_sources[0x23] 2463 1 T40 1 T84 1 T14 207
valid_sources[0x24] 2642 1 T46 1 T85 3 T86 96
valid_sources[0x25] 2027 1 T36 3 T39 12 T14 137
valid_sources[0x26] 2980 1 T36 4 T38 7 T129 2
valid_sources[0x27] 2184 1 T36 1 T83 2 T85 3
valid_sources[0x28] 2682 1 T82 2 T83 1 T42 1
valid_sources[0x29] 2646 1 T84 1 T132 2 T14 179
valid_sources[0x2a] 2685 1 T85 1 T14 171 T15 157
valid_sources[0x2b] 3015 1 T46 2 T38 2 T84 1
valid_sources[0x2c] 2442 1 T25 1 T36 2 T130 1
valid_sources[0x2d] 1991 1 T20 1 T84 2 T45 1
valid_sources[0x2e] 2663 1 T38 1 T83 1 T14 154
valid_sources[0x2f] 2043 1 T2 1 T10 1 T38 2
valid_sources[0x30] 2658 1 T7 1 T46 1 T38 1
valid_sources[0x31] 2089 1 T84 2 T14 160 T15 178
valid_sources[0x32] 2515 1 T38 1 T43 1 T45 1
valid_sources[0x33] 2136 1 T38 2 T42 1 T14 170
valid_sources[0x34] 2226 1 T38 2 T129 1 T83 1
valid_sources[0x35] 2289 1 T3 1 T4 1 T14 185
valid_sources[0x36] 2711 1 T17 1 T24 3 T14 197
valid_sources[0x37] 2163 1 T38 1 T85 2 T132 1
valid_sources[0x38] 3093 1 T24 2 T36 1 T135 1
valid_sources[0x39] 3292 1 T36 2 T38 2 T129 2
valid_sources[0x3a] 2499 1 T36 1 T42 1 T85 1
valid_sources[0x3b] 2336 1 T17 1 T46 1 T36 1
valid_sources[0x3c] 2517 1 T66 1 T36 3 T44 1
valid_sources[0x3d] 2485 1 T20 1 T36 2 T38 1
valid_sources[0x3e] 3137 1 T38 1 T84 1 T14 181
valid_sources[0x3f] 2341 1 T2 1 T36 2 T14 178
valid_sources[0x40] 2282 1 T38 2 T14 179 T15 377
valid_sources[0x41] 2692 1 T36 1 T84 2 T85 5
valid_sources[0x42] 1987 1 T46 1 T38 2 T40 1
valid_sources[0x43] 3054 1 T127 1 T45 1 T14 176
valid_sources[0x44] 2404 1 T28 1 T46 1 T43 1
valid_sources[0x45] 2557 1 T24 1 T36 1 T67 4
valid_sources[0x46] 2792 1 T2 1 T10 1 T42 1
valid_sources[0x47] 3016 1 T17 3 T132 1 T14 190
valid_sources[0x48] 2094 1 T24 1 T36 1 T38 2
valid_sources[0x49] 2726 1 T85 6 T14 180 T58 1
valid_sources[0x4a] 2565 1 T17 2 T24 2 T129 1
valid_sources[0x4b] 3129 1 T2 1 T44 1 T45 1
valid_sources[0x4c] 2203 1 T3 3 T14 184 T57 1
valid_sources[0x4d] 2546 1 T38 2 T14 204 T15 242
valid_sources[0x4e] 2212 1 T38 2 T129 1 T45 1
valid_sources[0x4f] 2037 1 T36 2 T14 200 T15 289
valid_sources[0x50] 2249 1 T24 1 T127 1 T85 3
valid_sources[0x51] 3319 1 T20 1 T46 1 T129 1
valid_sources[0x52] 1858 1 T36 3 T14 190 T15 193
valid_sources[0x53] 2241 1 T46 1 T40 1 T14 170
valid_sources[0x54] 2565 1 T67 3 T85 3 T132 6
valid_sources[0x55] 2099 1 T36 1 T38 2 T14 172
valid_sources[0x56] 2189 1 T38 3 T82 1 T85 3
valid_sources[0x57] 3144 1 T2 1 T5 1 T85 3
valid_sources[0x58] 2428 1 T67 1 T132 2 T14 182
valid_sources[0x59] 2240 1 T14 161 T55 1 T15 249
valid_sources[0x5a] 2058 1 T3 2 T36 1 T38 2
valid_sources[0x5b] 2936 1 T2 1 T38 2 T84 1
valid_sources[0x5c] 2887 1 T46 1 T85 2 T14 190
valid_sources[0x5d] 2610 1 T84 2 T132 2 T14 164
valid_sources[0x5e] 2449 1 T3 1 T8 11 T129 3
valid_sources[0x5f] 2228 1 T3 2 T129 1 T67 2
valid_sources[0x60] 2541 1 T20 1 T38 1 T14 171
valid_sources[0x61] 2326 1 T24 1 T85 3 T14 189
valid_sources[0x62] 2229 1 T20 1 T83 1 T84 1
valid_sources[0x63] 2545 1 T84 3 T43 2 T14 180
valid_sources[0x64] 2775 1 T36 2 T38 4 T127 1
valid_sources[0x65] 2460 1 T2 1 T40 1 T83 1
valid_sources[0x66] 1842 1 T25 3 T36 1 T85 1
valid_sources[0x67] 2067 1 T38 1 T14 178 T15 290
valid_sources[0x68] 2057 1 T85 2 T132 1 T14 165
valid_sources[0x69] 2677 1 T38 1 T127 2 T85 6
valid_sources[0x6a] 2871 1 T85 1 T14 163 T58 1
valid_sources[0x6b] 3266 1 T24 1 T41 9 T83 1
valid_sources[0x6c] 2371 1 T17 1 T36 1 T85 3
valid_sources[0x6d] 2143 1 T3 3 T38 1 T39 20
valid_sources[0x6e] 2942 1 T84 1 T43 1 T14 173
valid_sources[0x6f] 1857 1 T36 2 T38 1 T40 1
valid_sources[0x70] 2289 1 T46 2 T14 174 T58 1
valid_sources[0x71] 2458 1 T36 1 T38 1 T40 1
valid_sources[0x72] 2342 1 T129 1 T14 165 T15 230
valid_sources[0x73] 2791 1 T40 1 T14 161 T58 1
valid_sources[0x74] 2203 1 T34 1 T36 2 T85 1
valid_sources[0x75] 2985 1 T132 1 T14 196 T15 340
valid_sources[0x76] 2107 1 T9 1 T20 1 T38 1
valid_sources[0x77] 2581 1 T36 1 T84 1 T14 181
valid_sources[0x78] 2430 1 T38 1 T43 1 T44 1
valid_sources[0x79] 2504 1 T38 3 T84 1 T44 2
valid_sources[0x7a] 1979 1 T14 163 T15 192 T69 1
valid_sources[0x7b] 2532 1 T17 1 T24 5 T46 1
valid_sources[0x7c] 2333 1 T14 202 T15 220 T136 1
valid_sources[0x7d] 1861 1 T36 1 T38 1 T83 1
valid_sources[0x7e] 2078 1 T42 1 T44 1 T127 1
valid_sources[0x7f] 2410 1 T17 2 T38 3 T14 150
valid_sources[0x80] 2811 1 T36 2 T84 1 T14 163



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 141268 1 T1 14 T2 16 T3 22
values[0x0] all_enables biggest_size 207845 1 T7 1 T8 5 T10 1
values[0x1] all_enables biggest_size 207214 1 T46 2 T67 3 T68 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%