Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1302095

1

T1

76

T2

61

T3

87

full_word

840429

1

T1

15

T2

8

T3

7

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2142214	1			T1	91		T2	69		T3	94
auto[TlIntgErrCmd]	112	1			T53	10		T54	5		T63	5
auto[TlIntgErrData]	95	1			T53	6		T54	7		T63	3
auto[TlIntgErrBoth]	103	1			T53	4		T54	8		T63	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

353293

1

T1

91

T2

69

T3

94

auto[1]

1789231

1

T14

137286

T15

184137

T16

152201

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	152985	1			T1	76		T2	61		T3	87
auto[TlIntgErrNone]	partial	auto[1]	1148828	1			T14	90289		T15	118378		T16	98080
auto[TlIntgErrNone]	full_word	auto[0]	200177	1			T1	15		T2	8		T3	7
auto[TlIntgErrNone]	full_word	auto[1]	640224	1			T14	46997		T15	65759		T16	54121
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T53	2		T54	2		T63	3
auto[TlIntgErrCmd]	partial	auto[1]	67	1			T53	8		T54	2		T63	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T115	1		T122	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T54	1		T117	2		T123	1
auto[TlIntgErrData]	partial	auto[0]	43	1			T53	5		T54	5		T63	1
auto[TlIntgErrData]	partial	auto[1]	44	1			T54	2		T63	1		T115	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T124	1		T119	1		T120	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T53	1		T63	1		T124	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T54	2		T63	1		T115	2
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T53	4		T54	5		T63	1
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T117	3		T121	1		T120	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T54	1		T124	1		T125	1