SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
87.50 | 87.50 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
rom_ctrl_tlul_cg | 87.50 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
87.50 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 1 | 7 | 87.50 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_regs_req_check | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 | |
cp_rom_invalid_condition | 2 | 1 | 1 | 50.00 | 100 | 1 | 1 | 0 | |
cp_rom_req_check | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
req_after_done | 2180486 | 1 | T3 | 32 | T4 | 3 | T6 | 32 | ||||
req_and_done | 14 | 1 | T40 | 1 | T41 | 1 | T101 | 1 | ||||
req_before_done | 13 | 1 | T11 | 1 | T12 | 1 | T42 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
check_invalid | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
check_valid | 327911794 | 1 | T1 | 181373 | T2 | 204576 | T3 | 443337 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
req_after_done | 2581194 | 1 | T1 | 4 | T3 | 76 | T4 | 3 | ||||
req_and_done | 71 | 1 | T1 | 1 | T8 | 1 | T19 | 1 | ||||
req_before_done | 281 | 1 | T3 | 2 | T6 | 2 | T14 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |