Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	51616	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1000358

1

T1

18

T3

8

T4

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	283624	1			T1	200		T3	88		T4	3
values[0x0]	376924	1			T11	36345		T12	25045		T13	17901
values[0x1]	391426	1			T11	37624		T12	25895		T13	18418

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25976	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1025998

1

T1

117

T3

65

T4

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3837	1			T22	1		T99	1		T15	2
valid_sources[0x01]	4019	1			T1	1		T8	1		T99	5
valid_sources[0x02]	3724	1			T6	1		T8	1		T99	1
valid_sources[0x03]	3904	1			T8	3		T15	2		T11	371
valid_sources[0x04]	4036	1			T1	1		T18	1		T99	1
valid_sources[0x05]	3997	1			T99	4		T115	2		T11	408
valid_sources[0x06]	4597	1			T1	1		T8	6		T97	30
valid_sources[0x07]	4086	1			T8	2		T16	3		T115	2
valid_sources[0x08]	3894	1			T99	6		T100	1		T115	1
valid_sources[0x09]	3931	1			T1	3		T6	1		T22	1
valid_sources[0x0a]	4037	1			T20	2		T21	1		T22	1
valid_sources[0x0b]	4467	1			T1	4		T8	1		T19	49
valid_sources[0x0c]	4033	1			T1	1		T7	1		T20	5
valid_sources[0x0d]	4395	1			T22	1		T16	1		T17	1
valid_sources[0x0e]	3867	1			T21	1		T115	2		T116	1
valid_sources[0x0f]	4246	1			T8	3		T21	2		T100	2
valid_sources[0x10]	4087	1			T6	1		T99	10		T75	3
valid_sources[0x11]	4013	1			T1	1		T22	2		T99	5
valid_sources[0x12]	4086	1			T1	3		T6	1		T8	2
valid_sources[0x13]	3617	1			T99	1		T16	1		T115	1
valid_sources[0x14]	4048	1			T1	3		T16	1		T76	5
valid_sources[0x15]	4393	1			T1	2		T19	19		T99	3
valid_sources[0x16]	3759	1			T1	7		T22	1		T16	1
valid_sources[0x17]	3995	1			T6	2		T21	3		T16	1
valid_sources[0x18]	4031	1			T1	1		T76	3		T11	372
valid_sources[0x19]	3987	1			T1	1		T20	13		T22	1
valid_sources[0x1a]	3865	1			T1	1		T99	4		T15	1
valid_sources[0x1b]	3769	1			T6	1		T21	3		T11	395
valid_sources[0x1c]	3858	1			T3	24		T8	4		T20	4
valid_sources[0x1d]	4453	1			T8	5		T20	7		T97	15
valid_sources[0x1e]	3926	1			T8	2		T21	1		T22	1
valid_sources[0x1f]	4117	1			T20	6		T21	14		T97	88
valid_sources[0x20]	4375	1			T1	1		T15	1		T16	1
valid_sources[0x21]	4565	1			T1	1		T20	3		T21	1
valid_sources[0x22]	4131	1			T75	4		T100	2		T116	3
valid_sources[0x23]	3882	1			T1	5		T21	2		T15	1
valid_sources[0x24]	4050	1			T4	1		T8	3		T99	4
valid_sources[0x25]	4055	1			T1	1		T6	2		T22	1
valid_sources[0x26]	3825	1			T22	1		T15	1		T100	1
valid_sources[0x27]	5294	1			T16	3		T75	1		T100	1
valid_sources[0x28]	3992	1			T1	2		T21	2		T99	3
valid_sources[0x29]	3869	1			T1	3		T22	1		T99	4
valid_sources[0x2a]	3744	1			T6	1		T8	2		T20	1
valid_sources[0x2b]	4054	1			T8	1		T99	2		T100	1
valid_sources[0x2c]	4145	1			T1	1		T22	1		T97	24
valid_sources[0x2d]	4215	1			T98	12		T15	1		T16	1
valid_sources[0x2e]	3932	1			T1	5		T20	3		T16	1
valid_sources[0x2f]	4271	1			T8	2		T21	5		T22	1
valid_sources[0x30]	3919	1			T1	1		T20	9		T16	3
valid_sources[0x31]	3925	1			T1	3		T8	3		T76	1
valid_sources[0x32]	3901	1			T99	5		T115	2		T11	365
valid_sources[0x33]	3883	1			T8	2		T20	2		T16	3
valid_sources[0x34]	4078	1			T76	4		T116	1		T11	390
valid_sources[0x35]	4152	1			T116	4		T11	380		T117	2
valid_sources[0x36]	4104	1			T8	2		T20	6		T99	7
valid_sources[0x37]	3927	1			T99	5		T17	2		T115	2
valid_sources[0x38]	3907	1			T1	1		T22	1		T99	1
valid_sources[0x39]	3822	1			T21	9		T99	2		T15	1
valid_sources[0x3a]	3756	1			T8	4		T20	1		T99	1
valid_sources[0x3b]	4788	1			T1	2		T8	7		T14	19
valid_sources[0x3c]	3791	1			T1	3		T6	1		T22	1
valid_sources[0x3d]	4200	1			T1	2		T99	3		T16	2
valid_sources[0x3e]	3999	1			T7	1		T21	2		T99	2
valid_sources[0x3f]	3987	1			T100	1		T115	2		T116	3
valid_sources[0x40]	3838	1			T21	1		T99	4		T15	2
valid_sources[0x41]	4086	1			T21	14		T22	1		T99	2
valid_sources[0x42]	4316	1			T15	1		T16	5		T11	403
valid_sources[0x43]	4328	1			T1	3		T16	1		T115	9
valid_sources[0x44]	4018	1			T99	4		T115	1		T11	379
valid_sources[0x45]	4971	1			T1	1		T99	2		T16	1
valid_sources[0x46]	4714	1			T1	1		T21	2		T99	3
valid_sources[0x47]	4129	1			T19	16		T11	374		T50	1
valid_sources[0x48]	3850	1			T1	2		T6	1		T99	3
valid_sources[0x49]	4164	1			T8	1		T100	2		T11	414
valid_sources[0x4a]	4193	1			T1	5		T6	2		T21	2
valid_sources[0x4b]	3655	1			T22	1		T99	4		T11	361
valid_sources[0x4c]	4043	1			T1	1		T20	6		T99	6
valid_sources[0x4d]	3874	1			T99	2		T17	7		T11	385
valid_sources[0x4e]	3889	1			T6	1		T20	1		T15	2
valid_sources[0x4f]	4062	1			T4	2		T20	9		T76	1
valid_sources[0x50]	3893	1			T8	4		T21	2		T22	1
valid_sources[0x51]	3938	1			T15	3		T16	2		T115	2
valid_sources[0x52]	3960	1			T8	4		T97	11		T99	2
valid_sources[0x53]	4589	1			T1	3		T21	1		T22	1
valid_sources[0x54]	4602	1			T6	1		T8	2		T99	2
valid_sources[0x55]	4676	1			T1	2		T11	379		T49	2
valid_sources[0x56]	3938	1			T7	1		T8	2		T20	3
valid_sources[0x57]	4260	1			T16	1		T11	416		T54	4
valid_sources[0x58]	4393	1			T99	1		T76	3		T115	2
valid_sources[0x59]	3855	1			T6	1		T99	2		T16	1
valid_sources[0x5a]	4099	1			T1	1		T8	4		T20	3
valid_sources[0x5b]	4987	1			T6	1		T8	2		T21	2
valid_sources[0x5c]	4114	1			T20	7		T22	1		T15	1
valid_sources[0x5d]	4222	1			T8	1		T22	2		T99	2
valid_sources[0x5e]	3882	1			T1	1		T20	11		T21	5
valid_sources[0x5f]	3963	1			T1	1		T8	1		T20	4
valid_sources[0x60]	4389	1			T1	6		T15	1		T116	1
valid_sources[0x61]	4115	1			T1	1		T8	4		T115	1
valid_sources[0x62]	3933	1			T8	2		T21	2		T99	4
valid_sources[0x63]	3894	1			T1	1		T8	2		T20	1
valid_sources[0x64]	4704	1			T8	5		T21	7		T11	370
valid_sources[0x65]	3917	1			T1	2		T6	1		T8	3
valid_sources[0x66]	4048	1			T1	1		T19	36		T18	4
valid_sources[0x67]	3956	1			T19	61		T22	1		T97	34
valid_sources[0x68]	5322	1			T1	1		T8	1		T100	3
valid_sources[0x69]	3895	1			T21	4		T99	1		T16	2
valid_sources[0x6a]	4747	1			T6	1		T8	1		T99	5
valid_sources[0x6b]	4192	1			T1	3		T99	1		T16	2
valid_sources[0x6c]	4786	1			T1	4		T11	367		T54	1
valid_sources[0x6d]	4403	1			T6	1		T20	2		T99	2
valid_sources[0x6e]	4582	1			T8	8		T11	368		T50	1
valid_sources[0x6f]	4131	1			T1	3		T22	1		T99	1
valid_sources[0x70]	3902	1			T99	1		T76	3		T115	1
valid_sources[0x71]	4583	1			T99	2		T16	1		T11	383
valid_sources[0x72]	4063	1			T1	3		T8	3		T97	36
valid_sources[0x73]	3986	1			T8	2		T21	12		T99	2
valid_sources[0x74]	4214	1			T116	1		T11	356		T53	8
valid_sources[0x75]	4122	1			T22	1		T99	4		T11	426
valid_sources[0x76]	3877	1			T6	1		T8	2		T99	2
valid_sources[0x77]	3810	1			T15	1		T100	1		T17	2
valid_sources[0x78]	4351	1			T1	1		T100	1		T76	5
valid_sources[0x79]	4184	1			T1	1		T8	1		T99	1
valid_sources[0x7a]	3843	1			T1	1		T99	1		T15	1
valid_sources[0x7b]	5395	1			T15	1		T16	2		T115	4
valid_sources[0x7c]	4095	1			T1	4		T8	1		T99	2
valid_sources[0x7d]	3922	1			T8	2		T20	3		T115	1
valid_sources[0x7e]	4022	1			T1	2		T22	1		T15	1
valid_sources[0x7f]	4400	1			T15	1		T11	397		T54	1
valid_sources[0x80]	4533	1			T1	2		T8	6		T99	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

252292

1

T1

18

T3

8

T4

3

values[0x0]

all_enables

biggest_size

373659

1

T11

36061

T12

24844

T13

17757

values[0x1]

all_enables

biggest_size

374407

1

T11

36101

T12

24775

T13

17619

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	77269	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

778920

1

T2

3

T3

18

T4

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	217508	1			T3	32		T4	12		T5	10
values[0x0]	297177	1			T2	3		T9	3		T25	7
values[0x1]	341504	1			T2	5		T9	7		T25	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35958	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

820231

1

T2

5

T3

21

T4

8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3503	1			T11	328		T32	18		T117	2
valid_sources[0x01]	3329	1			T25	1		T100	1		T11	298
valid_sources[0x02]	3102	1			T7	1		T11	311		T118	4
valid_sources[0x03]	3437	1			T62	1		T11	299		T119	1
valid_sources[0x04]	3399	1			T25	1		T11	313		T120	6
valid_sources[0x05]	2950	1			T7	1		T38	1		T11	317
valid_sources[0x06]	3391	1			T58	1		T11	312		T121	1
valid_sources[0x07]	3277	1			T15	1		T100	1		T11	297
valid_sources[0x08]	3456	1			T100	2		T11	305		T48	8
valid_sources[0x09]	3090	1			T18	1		T11	278		T54	1
valid_sources[0x0a]	3040	1			T4	1		T30	1		T11	282
valid_sources[0x0b]	2926	1			T11	310		T122	4		T123	1
valid_sources[0x0c]	3471	1			T11	331		T124	1		T119	1
valid_sources[0x0d]	3281	1			T18	1		T11	305		T53	1
valid_sources[0x0e]	3277	1			T30	1		T11	317		T54	1
valid_sources[0x0f]	3282	1			T7	1		T11	280		T119	1
valid_sources[0x10]	3660	1			T3	4		T11	290		T122	1
valid_sources[0x11]	3628	1			T7	2		T11	306		T124	1
valid_sources[0x12]	3175	1			T125	1		T11	316		T54	1
valid_sources[0x13]	3685	1			T11	326		T123	2		T126	13
valid_sources[0x14]	2708	1			T25	1		T125	1		T11	329
valid_sources[0x15]	3319	1			T58	1		T30	2		T15	1
valid_sources[0x16]	3277	1			T11	305		T119	1		T123	1
valid_sources[0x17]	3392	1			T18	1		T11	314		T53	1
valid_sources[0x18]	3067	1			T18	2		T11	344		T119	1
valid_sources[0x19]	3516	1			T11	308		T53	1		T117	2
valid_sources[0x1a]	3483	1			T30	2		T11	332		T54	2
valid_sources[0x1b]	2952	1			T11	332		T121	1		T119	1
valid_sources[0x1c]	3583	1			T18	1		T15	1		T11	309
valid_sources[0x1d]	3301	1			T15	1		T11	313		T54	1
valid_sources[0x1e]	3685	1			T11	327		T53	1		T127	1
valid_sources[0x1f]	3276	1			T11	339		T119	2		T12	217
valid_sources[0x20]	3495	1			T15	1		T11	297		T117	1
valid_sources[0x21]	3037	1			T62	1		T11	289		T119	2
valid_sources[0x22]	3117	1			T11	290		T117	1		T121	2
valid_sources[0x23]	3467	1			T11	332		T49	19		T33	2
valid_sources[0x24]	3393	1			T11	317		T54	1		T77	1
valid_sources[0x25]	2883	1			T3	2		T62	1		T11	303
valid_sources[0x26]	3393	1			T100	3		T11	308		T53	1
valid_sources[0x27]	3204	1			T11	283		T117	1		T119	1
valid_sources[0x28]	2895	1			T11	268		T54	2		T124	1
valid_sources[0x29]	3468	1			T17	1		T11	296		T53	1
valid_sources[0x2a]	3187	1			T11	319		T51	1		T119	1
valid_sources[0x2b]	3726	1			T11	291		T54	1		T124	1
valid_sources[0x2c]	3407	1			T75	8		T11	292		T124	2
valid_sources[0x2d]	3416	1			T25	1		T30	1		T62	1
valid_sources[0x2e]	3017	1			T11	285		T54	1		T124	1
valid_sources[0x2f]	3457	1			T11	306		T63	2		T123	1
valid_sources[0x30]	3434	1			T100	1		T11	323		T53	1
valid_sources[0x31]	3323	1			T100	2		T62	1		T11	314
valid_sources[0x32]	3614	1			T11	309		T54	1		T119	1
valid_sources[0x33]	3651	1			T125	1		T11	328		T63	3
valid_sources[0x34]	3114	1			T100	3		T17	2		T11	310
valid_sources[0x35]	3233	1			T9	1		T11	287		T123	1
valid_sources[0x36]	3369	1			T4	2		T30	3		T11	319
valid_sources[0x37]	3326	1			T11	334		T54	1		T128	1
valid_sources[0x38]	3487	1			T11	280		T124	3		T35	1
valid_sources[0x39]	3519	1			T15	3		T11	305		T54	1
valid_sources[0x3a]	3238	1			T11	293		T54	1		T119	2
valid_sources[0x3b]	3606	1			T7	1		T11	318		T117	1
valid_sources[0x3c]	3423	1			T14	32		T11	294		T119	1
valid_sources[0x3d]	3577	1			T11	290		T53	1		T63	1
valid_sources[0x3e]	3350	1			T3	2		T11	333		T54	1
valid_sources[0x3f]	3368	1			T25	1		T62	1		T11	291
valid_sources[0x40]	3572	1			T11	293		T53	1		T122	5
valid_sources[0x41]	3339	1			T11	330		T35	1		T123	2
valid_sources[0x42]	3496	1			T11	322		T49	8		T54	1
valid_sources[0x43]	3411	1			T11	317		T53	1		T117	2
valid_sources[0x44]	3487	1			T100	1		T11	309		T54	1
valid_sources[0x45]	3111	1			T15	1		T11	260		T49	5
valid_sources[0x46]	3341	1			T11	329		T54	1		T119	3
valid_sources[0x47]	3795	1			T11	295		T119	1		T123	1
valid_sources[0x48]	3240	1			T125	1		T11	292		T54	1
valid_sources[0x49]	3651	1			T18	3		T11	296		T119	1
valid_sources[0x4a]	3606	1			T3	1		T11	285		T54	1
valid_sources[0x4b]	3404	1			T17	7		T11	302		T117	1
valid_sources[0x4c]	3283	1			T4	1		T25	1		T11	323
valid_sources[0x4d]	3147	1			T11	311		T121	2		T119	1
valid_sources[0x4e]	3162	1			T7	1		T11	294		T53	1
valid_sources[0x4f]	3256	1			T15	2		T11	332		T119	1
valid_sources[0x50]	3533	1			T4	1		T23	20		T11	298
valid_sources[0x51]	3310	1			T11	329		T53	1		T119	2
valid_sources[0x52]	3447	1			T11	319		T123	2		T12	205
valid_sources[0x53]	3084	1			T11	313		T53	1		T12	219
valid_sources[0x54]	3211	1			T100	1		T11	311		T54	1
valid_sources[0x55]	3158	1			T18	1		T11	294		T117	1
valid_sources[0x56]	3803	1			T6	32		T17	1		T11	321
valid_sources[0x57]	3299	1			T30	3		T11	271		T119	2
valid_sources[0x58]	3241	1			T25	1		T11	329		T117	1
valid_sources[0x59]	3261	1			T11	299		T129	1		T12	220
valid_sources[0x5a]	3529	1			T11	294		T53	1		T123	1
valid_sources[0x5b]	3338	1			T2	8		T58	2		T76	1
valid_sources[0x5c]	2936	1			T11	296		T53	2		T122	1
valid_sources[0x5d]	3684	1			T11	291		T119	2		T130	1
valid_sources[0x5e]	3242	1			T3	1		T11	303		T119	1
valid_sources[0x5f]	3333	1			T7	1		T76	5		T11	263
valid_sources[0x60]	3557	1			T18	1		T11	295		T53	1
valid_sources[0x61]	3170	1			T11	317		T119	1		T129	1
valid_sources[0x62]	3273	1			T11	274		T118	1		T131	1
valid_sources[0x63]	3309	1			T11	302		T117	1		T123	1
valid_sources[0x64]	3344	1			T15	1		T16	96		T100	1
valid_sources[0x65]	3310	1			T75	24		T11	304		T77	2
valid_sources[0x66]	3261	1			T7	3		T15	1		T11	301
valid_sources[0x67]	3458	1			T17	2		T11	328		T131	1
valid_sources[0x68]	3346	1			T4	1		T11	309		T119	1
valid_sources[0x69]	3297	1			T3	6		T18	1		T11	302
valid_sources[0x6a]	3144	1			T11	339		T132	2		T35	1
valid_sources[0x6b]	3293	1			T18	1		T11	290		T12	240
valid_sources[0x6c]	3673	1			T62	1		T11	288		T53	1
valid_sources[0x6d]	3784	1			T11	294		T53	1		T117	1
valid_sources[0x6e]	3840	1			T11	316		T53	1		T133	3
valid_sources[0x6f]	3465	1			T62	1		T11	310		T119	2
valid_sources[0x70]	3396	1			T11	326		T124	1		T119	3
valid_sources[0x71]	3443	1			T18	1		T11	317		T54	2
valid_sources[0x72]	3188	1			T11	289		T54	3		T124	3
valid_sources[0x73]	3175	1			T18	1		T15	1		T11	282
valid_sources[0x74]	3677	1			T11	317		T53	1		T130	1
valid_sources[0x75]	2931	1			T58	1		T11	295		T53	1
valid_sources[0x76]	3065	1			T134	1		T11	317		T119	2
valid_sources[0x77]	3497	1			T17	5		T11	297		T53	1
valid_sources[0x78]	3320	1			T11	296		T119	1		T122	5
valid_sources[0x79]	3468	1			T4	1		T18	1		T58	1
valid_sources[0x7a]	3294	1			T25	1		T11	295		T54	1
valid_sources[0x7b]	3022	1			T11	274		T117	1		T64	1
valid_sources[0x7c]	3498	1			T7	2		T15	1		T11	329
valid_sources[0x7d]	3544	1			T15	1		T11	320		T119	1
valid_sources[0x7e]	3223	1			T11	294		T77	5		T122	6
valid_sources[0x7f]	3168	1			T15	1		T11	308		T135	1
valid_sources[0x80]	3232	1			T18	1		T100	2		T11	326

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

198014

1

T3

18

T4

7

T6

21

values[0x0]

all_enables

biggest_size

291074

1

T2

2

T25

3

T58

3

values[0x1]

all_enables

biggest_size

289832

1

T2

1

T62

1

T11

26821