Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1838742

1

T1

182

T3

80

T6

47

full_word

1168336

1

T1

18

T3

8

T4

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3006778	1			T1	200		T3	88		T4	2
auto[TlIntgErrCmd]	93	1			T55	4		T56	8		T57	4
auto[TlIntgErrData]	108	1			T55	2		T56	8		T57	8
auto[TlIntgErrBoth]	99	1			T55	4		T56	4		T57	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

489500

1

T1

200

T3

88

T4

2

auto[1]

2517578

1

T11

235354

T12

165491

T13

118261

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	212359	1			T1	182		T3	80		T6	47
auto[TlIntgErrNone]	partial	auto[1]	1626113	1			T11	149779		T12	106355		T13	76189
auto[TlIntgErrNone]	full_word	auto[0]	277004	1			T1	18		T3	8		T4	2
auto[TlIntgErrNone]	full_word	auto[1]	891302	1			T11	85575		T12	59136		T13	42072
auto[TlIntgErrCmd]	partial	auto[0]	31	1			T55	1		T57	1		T112	3
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T55	2		T56	6		T57	2
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T55	1		T110	1		T107	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T56	2		T57	1		T105	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T55	1		T56	4		T57	4
auto[TlIntgErrData]	partial	auto[1]	48	1			T55	1		T56	2		T57	4
auto[TlIntgErrData]	full_word	auto[0]	6	1			T56	1		T110	1		T107	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T56	1		T109	1		T113	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T55	3		T56	2		T57	5
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T55	1		T56	2		T57	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T113	1		T103	1		T114	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T57	1		T114	1		-	-