Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 58982 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 1359913 1 T1 14 T2 2 T4 6



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 374271 1 T1 165 T2 84 T4 54
values[0x0] 513457 1 T12 69545 T13 33719 T15 21325
values[0x1] 531167 1 T12 72207 T13 34770 T15 21879



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 30199 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1388696 1 T1 96 T2 47 T4 33



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 5868 1 T9 2 T121 1 T75 3
valid_sources[0x01] 5405 1 T9 1 T122 16 T12 757
valid_sources[0x02] 5348 1 T7 2 T9 1 T74 1
valid_sources[0x03] 5324 1 T10 1 T121 2 T123 1
valid_sources[0x04] 5437 1 T2 3 T9 1 T124 3
valid_sources[0x05] 5076 1 T7 2 T124 4 T12 664
valid_sources[0x06] 5305 1 T10 1 T124 1 T75 14
valid_sources[0x07] 5664 1 T1 3 T9 3 T17 1
valid_sources[0x08] 5376 1 T1 16 T7 1 T10 3
valid_sources[0x09] 5325 1 T9 1 T18 5 T124 2
valid_sources[0x0a] 5645 1 T9 1 T124 4 T123 1
valid_sources[0x0b] 5399 1 T10 1 T121 1 T124 2
valid_sources[0x0c] 5466 1 T7 1 T9 2 T20 1
valid_sources[0x0d] 5207 1 T2 6 T7 2 T9 1
valid_sources[0x0e] 5175 1 T17 1 T124 2 T123 1
valid_sources[0x0f] 5933 1 T9 2 T124 2 T123 1
valid_sources[0x10] 5425 1 T2 1 T7 1 T9 1
valid_sources[0x11] 5346 1 T10 2 T74 1 T124 1
valid_sources[0x12] 5280 1 T2 2 T9 1 T10 2
valid_sources[0x13] 5578 1 T7 2 T9 1 T18 1
valid_sources[0x14] 5354 1 T7 1 T75 1 T125 1
valid_sources[0x15] 6267 1 T124 1 T75 2 T126 3
valid_sources[0x16] 6071 1 T1 13 T17 1 T124 2
valid_sources[0x17] 6559 1 T74 1 T124 1 T125 2
valid_sources[0x18] 5368 1 T7 1 T17 1 T124 3
valid_sources[0x19] 5563 1 T7 1 T18 1 T127 1
valid_sources[0x1a] 5387 1 T1 2 T9 2 T74 1
valid_sources[0x1b] 5191 1 T7 2 T9 2 T10 1
valid_sources[0x1c] 5484 1 T17 1 T74 2 T12 735
valid_sources[0x1d] 7412 1 T1 7 T9 6 T10 1
valid_sources[0x1e] 5846 1 T1 8 T9 2 T124 1
valid_sources[0x1f] 4969 1 T124 2 T128 4 T127 1
valid_sources[0x20] 5328 1 T7 1 T9 4 T121 1
valid_sources[0x21] 5253 1 T9 1 T10 2 T74 1
valid_sources[0x22] 5650 1 T7 1 T9 4 T10 3
valid_sources[0x23] 6121 1 T7 1 T10 1 T121 1
valid_sources[0x24] 5449 1 T10 1 T74 2 T124 2
valid_sources[0x25] 5838 1 T10 1 T121 1 T12 769
valid_sources[0x26] 5673 1 T7 2 T9 2 T125 1
valid_sources[0x27] 5234 1 T17 1 T121 2 T126 3
valid_sources[0x28] 5342 1 T7 1 T9 1 T74 2
valid_sources[0x29] 5346 1 T1 1 T9 1 T10 1
valid_sources[0x2a] 5212 1 T124 3 T125 2 T127 1
valid_sources[0x2b] 5543 1 T9 1 T18 1 T124 1
valid_sources[0x2c] 5414 1 T10 1 T18 1 T121 1
valid_sources[0x2d] 5450 1 T10 1 T121 1 T124 1
valid_sources[0x2e] 5762 1 T7 1 T121 3 T124 2
valid_sources[0x2f] 5308 1 T7 1 T9 9 T126 2
valid_sources[0x30] 5891 1 T10 2 T124 2 T126 1
valid_sources[0x31] 5561 1 T7 1 T17 1 T121 1
valid_sources[0x32] 5306 1 T9 5 T121 3 T124 4
valid_sources[0x33] 5834 1 T9 1 T124 2 T12 745
valid_sources[0x34] 6242 1 T9 2 T17 1 T19 1
valid_sources[0x35] 5904 1 T7 2 T9 4 T124 1
valid_sources[0x36] 5592 1 T74 1 T124 1 T12 753
valid_sources[0x37] 5264 1 T10 1 T18 2 T107 18
valid_sources[0x38] 5371 1 T7 4 T9 1 T10 1
valid_sources[0x39] 5199 1 T9 3 T124 1 T123 1
valid_sources[0x3a] 5504 1 T7 1 T124 1 T126 1
valid_sources[0x3b] 5243 1 T17 1 T74 1 T121 1
valid_sources[0x3c] 6054 1 T10 1 T17 1 T121 1
valid_sources[0x3d] 5077 1 T7 3 T9 3 T124 3
valid_sources[0x3e] 5477 1 T9 1 T121 1 T124 1
valid_sources[0x3f] 5767 1 T7 1 T9 1 T10 1
valid_sources[0x40] 5341 1 T4 10 T9 11 T121 2
valid_sources[0x41] 6155 1 T9 4 T17 1 T124 1
valid_sources[0x42] 5335 1 T7 1 T17 1 T74 1
valid_sources[0x43] 5377 1 T7 1 T10 1 T124 4
valid_sources[0x44] 5410 1 T2 8 T10 1 T121 1
valid_sources[0x45] 5287 1 T7 1 T17 1 T121 3
valid_sources[0x46] 5091 1 T10 1 T17 1 T74 2
valid_sources[0x47] 5341 1 T1 9 T7 3 T10 1
valid_sources[0x48] 5776 1 T10 1 T121 1 T128 1
valid_sources[0x49] 5665 1 T9 4 T124 1 T126 3
valid_sources[0x4a] 5434 1 T10 1 T18 1 T123 2
valid_sources[0x4b] 5836 1 T8 6 T9 2 T18 2
valid_sources[0x4c] 5027 1 T10 1 T12 727 T49 1
valid_sources[0x4d] 5534 1 T10 1 T18 1 T124 1
valid_sources[0x4e] 5481 1 T9 1 T123 1 T128 1
valid_sources[0x4f] 6236 1 T9 1 T10 1 T18 2
valid_sources[0x50] 5303 1 T9 1 T10 1 T124 1
valid_sources[0x51] 5768 1 T7 2 T18 5 T124 2
valid_sources[0x52] 5588 1 T7 3 T10 2 T124 3
valid_sources[0x53] 5260 1 T124 1 T123 1 T126 2
valid_sources[0x54] 6192 1 T10 1 T20 1 T124 1
valid_sources[0x55] 5477 1 T7 1 T9 1 T17 1
valid_sources[0x56] 5261 1 T9 2 T124 1 T123 3
valid_sources[0x57] 5509 1 T7 3 T9 2 T121 1
valid_sources[0x58] 5600 1 T124 3 T75 7 T123 2
valid_sources[0x59] 6090 1 T7 2 T121 1 T124 2
valid_sources[0x5a] 6521 1 T7 5 T9 1 T10 1
valid_sources[0x5b] 5301 1 T9 6 T126 2 T12 720
valid_sources[0x5c] 5246 1 T1 10 T9 7 T10 1
valid_sources[0x5d] 5952 1 T121 1 T124 1 T75 9
valid_sources[0x5e] 7421 1 T7 3 T121 1 T124 2
valid_sources[0x5f] 5532 1 T2 7 T9 4 T10 1
valid_sources[0x60] 5571 1 T9 4 T17 1 T121 2
valid_sources[0x61] 5344 1 T9 1 T123 1 T12 780
valid_sources[0x62] 5241 1 T107 24 T121 3 T124 1
valid_sources[0x63] 5509 1 T17 1 T121 3 T124 2
valid_sources[0x64] 6222 1 T7 4 T17 2 T124 3
valid_sources[0x65] 5194 1 T124 1 T75 4 T123 1
valid_sources[0x66] 5847 1 T121 1 T124 1 T126 1
valid_sources[0x67] 5328 1 T4 5 T9 2 T124 1
valid_sources[0x68] 5217 1 T17 1 T124 2 T126 1
valid_sources[0x69] 5568 1 T9 2 T10 1 T121 1
valid_sources[0x6a] 6312 1 T10 1 T18 1 T107 67
valid_sources[0x6b] 5353 1 T9 2 T124 2 T12 760
valid_sources[0x6c] 5244 1 T9 3 T31 9 T124 1
valid_sources[0x6d] 5579 1 T2 5 T9 5 T124 2
valid_sources[0x6e] 5196 1 T10 1 T17 1 T124 2
valid_sources[0x6f] 5378 1 T7 2 T10 1 T121 2
valid_sources[0x70] 5358 1 T9 1 T10 1 T18 1
valid_sources[0x71] 5786 1 T9 1 T10 1 T18 2
valid_sources[0x72] 6311 1 T1 14 T7 1 T10 1
valid_sources[0x73] 5432 1 T4 3 T17 1 T124 4
valid_sources[0x74] 5579 1 T7 4 T9 4 T10 1
valid_sources[0x75] 5169 1 T10 1 T121 1 T124 2
valid_sources[0x76] 5209 1 T9 3 T17 3 T74 1
valid_sources[0x77] 5524 1 T4 9 T7 3 T9 2
valid_sources[0x78] 5820 1 T9 5 T18 1 T124 2
valid_sources[0x79] 5332 1 T7 1 T74 1 T12 732
valid_sources[0x7a] 5726 1 T9 1 T124 1 T126 4
valid_sources[0x7b] 5174 1 T107 35 T124 1 T123 1
valid_sources[0x7c] 5127 1 T10 1 T17 1 T107 42
valid_sources[0x7d] 5631 1 T9 2 T18 2 T121 1
valid_sources[0x7e] 5426 1 T126 1 T125 4 T12 793
valid_sources[0x7f] 5889 1 T124 2 T123 1 T125 3
valid_sources[0x80] 5858 1 T18 4 T124 2 T12 778



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 342900 1 T1 14 T2 2 T4 6
values[0x0] all_enables biggest_size 509009 1 T12 68902 T13 33448 T15 21152
values[0x1] all_enables biggest_size 508004 1 T12 69061 T13 33235 T15 20996


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 106277 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 1053681 1 T1 32 T2 22 T4 20



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 290109 1 T1 64 T2 32 T4 32
values[0x0] 402340 1 T26 1 T23 4 T24 4
values[0x1] 467509 1 T3 1 T26 3 T23 6



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 47908 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1112050 1 T1 41 T2 24 T4 24



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 4188 1 T18 1 T23 10 T12 603
valid_sources[0x01] 4879 1 T31 1 T12 614 T13 171
valid_sources[0x02] 4274 1 T31 1 T24 2 T126 1
valid_sources[0x03] 3675 1 T1 1 T6 20 T8 2
valid_sources[0x04] 3669 1 T12 585 T13 2 T129 20
valid_sources[0x05] 5041 1 T9 1 T11 1 T75 6
valid_sources[0x06] 4735 1 T12 611 T130 3 T15 197
valid_sources[0x07] 4081 1 T12 629 T13 98 T36 1
valid_sources[0x08] 4364 1 T4 5 T8 2 T9 1
valid_sources[0x09] 4962 1 T12 602 T13 130 T131 1
valid_sources[0x0a] 5224 1 T126 1 T12 556 T49 2
valid_sources[0x0b] 3655 1 T9 4 T11 1 T75 3
valid_sources[0x0c] 4019 1 T12 598 T32 3 T13 303
valid_sources[0x0d] 5057 1 T9 1 T11 1 T74 32
valid_sources[0x0e] 3920 1 T9 1 T126 2 T12 590
valid_sources[0x0f] 4116 1 T1 1 T9 2 T75 1
valid_sources[0x10] 4438 1 T2 3 T9 1 T31 1
valid_sources[0x11] 4544 1 T9 1 T126 1 T12 572
valid_sources[0x12] 4315 1 T11 1 T75 2 T41 1
valid_sources[0x13] 3291 1 T9 1 T12 572 T13 108
valid_sources[0x14] 4544 1 T1 1 T75 1 T128 5
valid_sources[0x15] 3540 1 T75 3 T127 1 T12 569
valid_sources[0x16] 4794 1 T1 2 T75 4 T126 1
valid_sources[0x17] 4947 1 T11 1 T12 601 T13 12
valid_sources[0x18] 2717 1 T75 3 T126 1 T12 583
valid_sources[0x19] 4909 1 T75 1 T126 1 T12 615
valid_sources[0x1a] 5134 1 T9 1 T126 1 T12 591
valid_sources[0x1b] 4527 1 T12 572 T13 374 T33 1
valid_sources[0x1c] 5404 1 T1 2 T126 1 T12 621
valid_sources[0x1d] 3859 1 T9 2 T11 1 T126 1
valid_sources[0x1e] 4174 1 T1 2 T31 2 T12 578
valid_sources[0x1f] 4428 1 T126 2 T12 573 T13 205
valid_sources[0x20] 5393 1 T9 1 T31 2 T12 562
valid_sources[0x21] 4280 1 T75 3 T41 1 T127 1
valid_sources[0x22] 4338 1 T1 1 T9 1 T12 611
valid_sources[0x23] 4094 1 T1 2 T9 2 T12 620
valid_sources[0x24] 3764 1 T11 1 T127 1 T12 573
valid_sources[0x25] 7015 1 T31 2 T128 6 T12 610
valid_sources[0x26] 3787 1 T18 1 T12 562 T13 311
valid_sources[0x27] 5551 1 T75 3 T126 1 T12 594
valid_sources[0x28] 3804 1 T12 592 T51 1 T13 562
valid_sources[0x29] 4369 1 T9 1 T12 583 T51 2
valid_sources[0x2a] 4200 1 T9 1 T12 564 T13 173
valid_sources[0x2b] 4484 1 T12 560 T13 410 T15 177
valid_sources[0x2c] 3873 1 T12 638 T13 27 T132 1
valid_sources[0x2d] 5080 1 T1 1 T75 4 T12 588
valid_sources[0x2e] 3274 1 T75 1 T12 570 T13 80
valid_sources[0x2f] 4752 1 T2 6 T9 1 T18 1
valid_sources[0x30] 3930 1 T11 1 T12 561 T13 453
valid_sources[0x31] 4181 1 T2 4 T126 1 T12 619
valid_sources[0x32] 3579 1 T9 3 T18 2 T75 1
valid_sources[0x33] 4371 1 T12 557 T13 272 T15 186
valid_sources[0x34] 4657 1 T1 1 T9 2 T11 2
valid_sources[0x35] 4363 1 T11 1 T12 597 T13 387
valid_sources[0x36] 4500 1 T1 1 T9 1 T18 1
valid_sources[0x37] 4167 1 T11 1 T126 1 T12 578
valid_sources[0x38] 5132 1 T1 1 T12 609 T32 3
valid_sources[0x39] 4715 1 T12 597 T13 270 T15 191
valid_sources[0x3a] 5673 1 T75 1 T12 632 T32 1
valid_sources[0x3b] 4388 1 T1 1 T41 1 T12 582
valid_sources[0x3c] 5370 1 T75 1 T12 557 T13 312
valid_sources[0x3d] 5164 1 T127 2 T12 595 T13 218
valid_sources[0x3e] 4526 1 T9 3 T12 554 T13 351
valid_sources[0x3f] 6009 1 T9 1 T12 635 T54 1
valid_sources[0x40] 4959 1 T11 1 T12 612 T13 384
valid_sources[0x41] 4208 1 T1 1 T128 7 T12 565
valid_sources[0x42] 3983 1 T126 1 T12 602 T13 15
valid_sources[0x43] 6034 1 T1 2 T9 1 T12 651
valid_sources[0x44] 3689 1 T1 1 T18 1 T28 1
valid_sources[0x45] 6174 1 T126 1 T12 590 T49 1
valid_sources[0x46] 4374 1 T1 2 T5 1 T12 572
valid_sources[0x47] 4298 1 T31 1 T12 593 T13 442
valid_sources[0x48] 3888 1 T1 2 T11 1 T75 1
valid_sources[0x49] 4446 1 T12 592 T13 197 T132 8
valid_sources[0x4a] 4413 1 T75 2 T12 586 T13 7
valid_sources[0x4b] 4362 1 T12 604 T54 3 T15 173
valid_sources[0x4c] 4731 1 T9 1 T31 1 T12 611
valid_sources[0x4d] 5537 1 T9 1 T11 1 T31 1
valid_sources[0x4e] 4752 1 T9 2 T12 547 T13 146
valid_sources[0x4f] 4126 1 T1 1 T9 2 T11 2
valid_sources[0x50] 4616 1 T12 630 T13 406 T42 1
valid_sources[0x51] 3787 1 T11 1 T75 2 T12 566
valid_sources[0x52] 4170 1 T1 1 T2 6 T126 2
valid_sources[0x53] 3846 1 T31 1 T126 1 T12 610
valid_sources[0x54] 4559 1 T9 1 T11 1 T126 1
valid_sources[0x55] 4440 1 T12 559 T13 146 T130 1
valid_sources[0x56] 4715 1 T11 1 T12 538 T51 1
valid_sources[0x57] 5819 1 T75 1 T12 605 T13 865
valid_sources[0x58] 5426 1 T9 2 T18 1 T126 2
valid_sources[0x59] 4653 1 T11 1 T128 9 T126 2
valid_sources[0x5a] 4500 1 T12 590 T13 5 T34 2
valid_sources[0x5b] 3628 1 T1 1 T11 1 T12 557
valid_sources[0x5c] 4888 1 T126 1 T12 582 T13 316
valid_sources[0x5d] 4596 1 T8 5 T9 1 T11 2
valid_sources[0x5e] 5148 1 T8 1 T127 1 T12 585
valid_sources[0x5f] 5957 1 T1 3 T9 2 T18 1
valid_sources[0x60] 3479 1 T18 1 T12 602 T13 10
valid_sources[0x61] 3956 1 T1 1 T11 1 T127 3
valid_sources[0x62] 3379 1 T9 1 T11 1 T12 592
valid_sources[0x63] 4702 1 T1 2 T4 5 T31 1
valid_sources[0x64] 4720 1 T1 1 T9 2 T11 1
valid_sources[0x65] 5082 1 T8 1 T12 611 T51 1
valid_sources[0x66] 3938 1 T126 2 T12 609 T49 3
valid_sources[0x67] 4673 1 T12 627 T32 4 T13 9
valid_sources[0x68] 4972 1 T12 584 T13 401 T78 1
valid_sources[0x69] 6546 1 T9 1 T20 27 T12 583
valid_sources[0x6a] 4890 1 T9 1 T12 574 T13 401
valid_sources[0x6b] 4143 1 T9 1 T12 638 T54 1
valid_sources[0x6c] 5182 1 T128 10 T126 1 T12 588
valid_sources[0x6d] 4815 1 T12 567 T13 612 T78 1
valid_sources[0x6e] 3663 1 T9 1 T12 634 T13 8
valid_sources[0x6f] 4707 1 T9 1 T126 1 T12 573
valid_sources[0x70] 4988 1 T75 1 T12 604 T51 1
valid_sources[0x71] 4324 1 T26 1 T11 1 T31 1
valid_sources[0x72] 3496 1 T12 615 T51 1 T54 1
valid_sources[0x73] 4295 1 T1 1 T9 1 T12 614
valid_sources[0x74] 4879 1 T11 1 T12 554 T13 86
valid_sources[0x75] 3958 1 T9 2 T12 583 T32 3
valid_sources[0x76] 4073 1 T126 1 T12 573 T32 1
valid_sources[0x77] 4893 1 T12 589 T13 643 T21 4
valid_sources[0x78] 6672 1 T1 1 T12 587 T13 596
valid_sources[0x79] 3816 1 T12 564 T49 2 T13 167
valid_sources[0x7a] 4815 1 T12 609 T13 167 T36 1
valid_sources[0x7b] 5427 1 T31 1 T12 560 T13 327
valid_sources[0x7c] 6004 1 T1 1 T18 1 T126 1
valid_sources[0x7d] 6184 1 T9 1 T12 612 T13 581
valid_sources[0x7e] 3699 1 T9 1 T12 608 T13 2
valid_sources[0x7f] 4724 1 T9 1 T12 575 T13 151
valid_sources[0x80] 4752 1 T9 3 T126 2 T12 584



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 266444 1 T1 32 T2 22 T4 20
values[0x0] all_enables biggest_size 393752 1 T23 1 T24 2 T12 51865
values[0x1] all_enables biggest_size 393485 1 T24 2 T12 51887 T25 2

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