Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2493308

1

T1

151

T2

82

T4

48

full_word

1586655

1

T1

14

T2

2

T4

6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4079653	1			T1	165		T2	84		T4	54
auto[TlIntgErrCmd]	109	1			T56	10		T57	9		T58	6
auto[TlIntgErrData]	98	1			T56	7		T57	5		T58	7
auto[TlIntgErrBoth]	103	1			T56	3		T57	6		T58	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

652363

1

T1

165

T2

84

T4

54

auto[1]

3427600

1

T12

465860

T13

226133

T15

137579

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	276208	1			T1	151		T2	82		T4	48
auto[TlIntgErrNone]	partial	auto[1]	2216813	1			T12	301656		T13	146764		T15	87707
auto[TlIntgErrNone]	full_word	auto[0]	376013	1			T1	14		T2	2		T4	6
auto[TlIntgErrNone]	full_word	auto[1]	1210619	1			T12	164204		T13	79369		T15	49872
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T56	3		T57	3		T58	2
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T56	6		T57	6		T58	4
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T56	1		T109	1		T116	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T110	1		T117	2		-	-
auto[TlIntgErrData]	partial	auto[0]	48	1			T56	2		T57	2		T58	2
auto[TlIntgErrData]	partial	auto[1]	45	1			T56	4		T57	3		T58	5
auto[TlIntgErrData]	full_word	auto[0]	3	1			T112	1		T113	1		T118	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T56	1		T116	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T56	1		T57	3		T58	4
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T56	2		T57	3		T58	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T119	1		T111	1		T114	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T109	1		T108	1		T120	2