SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.rom_ctrl_regs_csr_assert | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
93.05 | 100.00 | 98.28 | 97.26 | 100.00 | 69.70 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
TlulOOBAddrErr_A | 374349029 | 1882235 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 374349029 | 1882235 | 0 | 0 |
T12 | 527117 | 246141 | 0 | 0 |
T13 | 0 | 129909 | 0 | 0 |
T15 | 0 | 73920 | 0 | 0 |
T16 | 0 | 362207 | 0 | 0 |
T25 | 107560 | 0 | 0 | 0 |
T32 | 458652 | 0 | 0 | 0 |
T43 | 0 | 114229 | 0 | 0 |
T44 | 0 | 180999 | 0 | 0 |
T45 | 0 | 134800 | 0 | 0 |
T46 | 0 | 77486 | 0 | 0 |
T47 | 0 | 119091 | 0 | 0 |
T48 | 0 | 78582 | 0 | 0 |
T49 | 754635 | 0 | 0 | 0 |
T50 | 410174 | 0 | 0 | 0 |
T51 | 672194 | 0 | 0 | 0 |
T52 | 371520 | 0 | 0 | 0 |
T53 | 556852 | 0 | 0 | 0 |
T54 | 363765 | 0 | 0 | 0 |
T55 | 155511 | 0 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |