Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1823253

1

T3

184

T4

183

T6

193

full_word

1176681

1

T1

6

T2

8

T3

26

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2999624	1			T1	6		T2	8		T3	210
auto[TlIntgErrCmd]	103	1			T60	9		T61	7		T62	2
auto[TlIntgErrData]	107	1			T60	5		T61	10		T62	8
auto[TlIntgErrBoth]	100	1			T60	6		T61	3		T109	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

488487

1

T1

6

T2

8

T3

210

auto[1]

2511447

1

T12

145094

T13

142062

T14

563698

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	209282	1			T3	184		T4	183		T6	193
auto[TlIntgErrNone]	partial	auto[1]	1613684	1			T12	92075		T13	93022		T14	362649
auto[TlIntgErrNone]	full_word	auto[0]	279058	1			T1	6		T2	8		T3	26
auto[TlIntgErrNone]	full_word	auto[1]	897600	1			T12	53019		T13	49040		T14	201049
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T60	3		T61	4		T109	4
auto[TlIntgErrCmd]	partial	auto[1]	49	1			T60	5		T61	3		T62	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T60	1		T109	1		T113	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T109	1		T114	1		T115	1
auto[TlIntgErrData]	partial	auto[0]	52	1			T60	3		T61	6		T62	1
auto[TlIntgErrData]	partial	auto[1]	48	1			T60	2		T61	4		T62	6
auto[TlIntgErrData]	full_word	auto[0]	3	1			T62	1		T110	1		T116	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T112	1		T117	1		T118	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T60	3		T61	1		T109	4
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T60	3		T61	2		T109	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T112	2		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T114	1		T119	1		T120	1