Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	56295	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1121571

1

T3

6

T5

37

T6

51619

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	315799	1			T3	6		T5	314		T6	14004
values[0x0]	423711	1			T6	19403		T11	31146		T22	17315
values[0x1]	438356	1			T6	20354		T11	32634		T22	17994

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28317	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1149549

1

T3

6

T5

205

T6

52621

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5666	1			T11	303		T83	1		T67	1
valid_sources[0x01]	5833	1			T6	145		T11	332		T96	1
valid_sources[0x02]	4839	1			T14	1		T15	2		T11	320
valid_sources[0x03]	4605	1			T6	262		T9	1		T11	345
valid_sources[0x04]	4467	1			T14	2		T11	329		T111	1
valid_sources[0x05]	3812	1			T11	318		T111	4		T83	2
valid_sources[0x06]	5357	1			T6	153		T11	343		T111	3
valid_sources[0x07]	3846	1			T11	336		T83	3		T112	1
valid_sources[0x08]	4607	1			T9	1		T11	325		T111	2
valid_sources[0x09]	5298	1			T11	343		T12	4		T96	1
valid_sources[0x0a]	5384	1			T6	252		T11	349		T83	2
valid_sources[0x0b]	5687	1			T7	5		T9	1		T11	339
valid_sources[0x0c]	3965	1			T6	34		T15	1		T11	334
valid_sources[0x0d]	4254	1			T8	4		T11	334		T64	6
valid_sources[0x0e]	5497	1			T6	82		T15	1		T11	338
valid_sources[0x0f]	5520	1			T11	317		T83	1		T113	2
valid_sources[0x10]	5298	1			T11	335		T85	2		T114	3
valid_sources[0x11]	5403	1			T6	144		T11	319		T96	1
valid_sources[0x12]	4251	1			T11	378		T66	2		T115	2
valid_sources[0x13]	6861	1			T6	963		T7	2		T15	1
valid_sources[0x14]	3755	1			T14	2		T11	324		T12	2
valid_sources[0x15]	5603	1			T6	39		T9	1		T15	1
valid_sources[0x16]	5562	1			T11	305		T53	1		T83	6
valid_sources[0x17]	3860	1			T11	328		T53	1		T113	1
valid_sources[0x18]	4059	1			T5	82		T9	1		T13	1
valid_sources[0x19]	3606	1			T6	72		T11	313		T83	1
valid_sources[0x1a]	3855	1			T6	189		T11	348		T83	2
valid_sources[0x1b]	5074	1			T15	3		T11	318		T53	1
valid_sources[0x1c]	4371	1			T11	329		T96	1		T111	1
valid_sources[0x1d]	4659	1			T6	39		T14	1		T11	327
valid_sources[0x1e]	4589	1			T6	961		T9	1		T15	2
valid_sources[0x1f]	5137	1			T8	1		T11	345		T53	1
valid_sources[0x20]	4914	1			T6	773		T14	3		T11	308
valid_sources[0x21]	4551	1			T6	829		T11	327		T85	1
valid_sources[0x22]	3738	1			T7	4		T11	329		T111	1
valid_sources[0x23]	3718	1			T11	345		T53	1		T96	1
valid_sources[0x24]	6602	1			T3	6		T11	329		T83	1
valid_sources[0x25]	5019	1			T6	112		T14	1		T11	346
valid_sources[0x26]	3917	1			T6	559		T11	313		T53	1
valid_sources[0x27]	5745	1			T6	99		T11	328		T113	3
valid_sources[0x28]	5168	1			T6	284		T11	359		T96	1
valid_sources[0x29]	5980	1			T6	437		T9	1		T11	388
valid_sources[0x2a]	4604	1			T6	253		T15	1		T11	361
valid_sources[0x2b]	6006	1			T9	1		T11	328		T83	4
valid_sources[0x2c]	4366	1			T6	61		T15	2		T11	349
valid_sources[0x2d]	3074	1			T14	1		T11	310		T12	2
valid_sources[0x2e]	4608	1			T6	357		T9	1		T11	317
valid_sources[0x2f]	4195	1			T15	1		T11	333		T84	1
valid_sources[0x30]	4420	1			T6	234		T11	347		T112	1
valid_sources[0x31]	4373	1			T11	343		T96	2		T83	2
valid_sources[0x32]	3103	1			T11	361		T83	2		T85	1
valid_sources[0x33]	3713	1			T5	80		T6	155		T15	1
valid_sources[0x34]	3848	1			T11	322		T54	16		T113	5
valid_sources[0x35]	3860	1			T6	87		T11	351		T83	1
valid_sources[0x36]	4103	1			T6	539		T11	318		T96	1
valid_sources[0x37]	4377	1			T6	116		T11	323		T113	2
valid_sources[0x38]	4393	1			T9	1		T11	330		T54	72
valid_sources[0x39]	3932	1			T8	3		T9	1		T11	326
valid_sources[0x3a]	4068	1			T6	303		T11	338		T83	2
valid_sources[0x3b]	4975	1			T6	205		T14	1		T11	327
valid_sources[0x3c]	4560	1			T15	1		T11	332		T83	2
valid_sources[0x3d]	4607	1			T6	615		T14	1		T11	322
valid_sources[0x3e]	4729	1			T5	11		T6	767		T7	1
valid_sources[0x3f]	4194	1			T6	167		T9	1		T11	333
valid_sources[0x40]	2979	1			T8	1		T9	1		T14	1
valid_sources[0x41]	4587	1			T11	279		T85	3		T113	3
valid_sources[0x42]	3946	1			T11	316		T83	1		T64	3
valid_sources[0x43]	3356	1			T5	10		T11	338		T53	1
valid_sources[0x44]	5963	1			T6	688		T11	325		T53	1
valid_sources[0x45]	4756	1			T6	601		T7	11		T9	1
valid_sources[0x46]	3679	1			T11	337		T111	1		T83	1
valid_sources[0x47]	4898	1			T6	499		T11	305		T83	1
valid_sources[0x48]	4262	1			T9	1		T15	1		T11	312
valid_sources[0x49]	3581	1			T11	335		T53	2		T96	1
valid_sources[0x4a]	3969	1			T6	478		T14	2		T11	330
valid_sources[0x4b]	5708	1			T6	119		T15	1		T11	306
valid_sources[0x4c]	3280	1			T14	1		T11	308		T111	1
valid_sources[0x4d]	3823	1			T6	286		T15	1		T11	327
valid_sources[0x4e]	6471	1			T6	529		T11	351		T83	5
valid_sources[0x4f]	4287	1			T6	298		T11	362		T54	41
valid_sources[0x50]	4267	1			T6	255		T14	2		T15	1
valid_sources[0x51]	5026	1			T6	531		T15	1		T11	285
valid_sources[0x52]	4367	1			T11	326		T53	1		T96	1
valid_sources[0x53]	4644	1			T6	886		T14	1		T15	2
valid_sources[0x54]	5118	1			T6	248		T11	321		T96	2
valid_sources[0x55]	5860	1			T6	1481		T7	1		T14	1
valid_sources[0x56]	3683	1			T14	1		T11	313		T83	1
valid_sources[0x57]	5138	1			T15	1		T11	328		T83	1
valid_sources[0x58]	4793	1			T6	158		T11	364		T111	1
valid_sources[0x59]	3894	1			T11	336		T53	1		T96	1
valid_sources[0x5a]	3998	1			T6	433		T11	309		T111	1
valid_sources[0x5b]	4161	1			T9	1		T15	1		T11	309
valid_sources[0x5c]	4675	1			T6	260		T11	309		T64	4
valid_sources[0x5d]	4039	1			T6	85		T14	1		T15	1
valid_sources[0x5e]	3272	1			T6	37		T15	1		T11	314
valid_sources[0x5f]	6614	1			T6	1241		T7	10		T11	319
valid_sources[0x60]	3882	1			T6	251		T14	1		T11	350
valid_sources[0x61]	6740	1			T6	154		T8	2		T11	329
valid_sources[0x62]	3496	1			T9	1		T11	352		T83	5
valid_sources[0x63]	4283	1			T6	144		T15	1		T11	318
valid_sources[0x64]	3624	1			T6	544		T8	6		T15	1
valid_sources[0x65]	4070	1			T6	19		T11	339		T83	1
valid_sources[0x66]	5252	1			T6	203		T14	1		T11	344
valid_sources[0x67]	3427	1			T14	1		T11	343		T53	1
valid_sources[0x68]	4174	1			T9	1		T11	319		T53	1
valid_sources[0x69]	5336	1			T15	1		T11	369		T53	2
valid_sources[0x6a]	4019	1			T6	146		T9	1		T11	315
valid_sources[0x6b]	4417	1			T6	63		T15	1		T11	360
valid_sources[0x6c]	4214	1			T6	310		T11	349		T111	1
valid_sources[0x6d]	4231	1			T11	324		T12	4		T83	3
valid_sources[0x6e]	4160	1			T6	138		T15	1		T11	304
valid_sources[0x6f]	4366	1			T6	116		T11	361		T53	1
valid_sources[0x70]	4123	1			T6	457		T15	1		T11	349
valid_sources[0x71]	5728	1			T8	5		T9	1		T14	1
valid_sources[0x72]	4779	1			T6	167		T14	1		T15	1
valid_sources[0x73]	4038	1			T15	1		T11	315		T111	2
valid_sources[0x74]	4701	1			T6	304		T9	1		T15	1
valid_sources[0x75]	4717	1			T6	194		T11	314		T64	1
valid_sources[0x76]	3811	1			T6	32		T11	353		T111	1
valid_sources[0x77]	4143	1			T6	604		T8	6		T9	1
valid_sources[0x78]	4786	1			T6	179		T11	327		T83	1
valid_sources[0x79]	5158	1			T6	111		T11	342		T111	1
valid_sources[0x7a]	4256	1			T6	81		T15	1		T11	335
valid_sources[0x7b]	3990	1			T15	1		T11	325		T96	1
valid_sources[0x7c]	3248	1			T15	1		T11	319		T84	8
valid_sources[0x7d]	3726	1			T14	1		T15	1		T11	352
valid_sources[0x7e]	5044	1			T6	1305		T11	349		T111	1
valid_sources[0x7f]	4403	1			T9	1		T15	2		T11	344
valid_sources[0x80]	4786	1			T11	310		T85	2		T113	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

282392

1

T3

6

T5

37

T6

13053

values[0x0]

all_enables

biggest_size

420008

1

T6

19210

T11

30877

T22

17150

values[0x1]

all_enables

biggest_size

419171

1

T6

19356

T11

31266

T22

17150

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	87718	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

857257

1

T1

1

T3

9

T6

40017

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	239537	1			T3	13		T4	10		T6	11056
values[0x0]	327379	1			T1	2		T2	1		T6	15370
values[0x1]	378059	1			T1	1		T6	17612		T17	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	40419	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

904556

1

T1

1

T3

9

T4

4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4067	1			T4	2		T6	166		T13	1
valid_sources[0x01]	3808	1			T6	161		T11	363		T116	1
valid_sources[0x02]	3391	1			T6	171		T11	305		T96	2
valid_sources[0x03]	3943	1			T6	192		T11	372		T67	3
valid_sources[0x04]	3359	1			T6	162		T9	11		T11	187
valid_sources[0x05]	3585	1			T6	171		T11	258		T30	1
valid_sources[0x06]	3832	1			T6	161		T11	178		T64	3
valid_sources[0x07]	3428	1			T6	168		T11	142		T68	1
valid_sources[0x08]	3880	1			T6	167		T11	289		T53	1
valid_sources[0x09]	3508	1			T6	154		T11	213		T116	2
valid_sources[0x0a]	3416	1			T6	161		T11	163		T22	238
valid_sources[0x0b]	3882	1			T6	208		T11	467		T84	2
valid_sources[0x0c]	3785	1			T6	180		T11	170		T66	1
valid_sources[0x0d]	3647	1			T6	149		T11	442		T84	1
valid_sources[0x0e]	3724	1			T6	179		T8	1		T11	236
valid_sources[0x0f]	3663	1			T6	172		T11	552		T64	4
valid_sources[0x10]	3496	1			T6	187		T10	1		T11	363
valid_sources[0x11]	3865	1			T6	158		T8	3		T13	2
valid_sources[0x12]	3504	1			T6	162		T11	189		T117	1
valid_sources[0x13]	3457	1			T6	190		T11	410		T118	2
valid_sources[0x14]	4011	1			T6	179		T11	246		T68	1
valid_sources[0x15]	3530	1			T6	165		T11	200		T96	2
valid_sources[0x16]	3896	1			T6	168		T11	163		T119	1
valid_sources[0x17]	3528	1			T6	165		T11	329		T84	1
valid_sources[0x18]	3487	1			T6	190		T11	267		T120	1
valid_sources[0x19]	3327	1			T6	168		T11	105		T121	1
valid_sources[0x1a]	3745	1			T6	174		T11	166		T122	1
valid_sources[0x1b]	3865	1			T6	161		T11	401		T120	1
valid_sources[0x1c]	3535	1			T6	164		T11	154		T66	1
valid_sources[0x1d]	3624	1			T6	181		T11	498		T116	1
valid_sources[0x1e]	3466	1			T6	169		T11	263		T84	1
valid_sources[0x1f]	3630	1			T4	1		T6	168		T11	210
valid_sources[0x20]	3612	1			T6	166		T11	156		T120	2
valid_sources[0x21]	3655	1			T6	161		T11	306		T115	1
valid_sources[0x22]	3305	1			T6	177		T11	223		T69	1
valid_sources[0x23]	3589	1			T6	171		T11	246		T120	1
valid_sources[0x24]	3469	1			T6	150		T11	262		T84	1
valid_sources[0x25]	3787	1			T6	174		T11	177		T69	1
valid_sources[0x26]	4161	1			T6	183		T11	440		T30	2
valid_sources[0x27]	3921	1			T6	165		T8	1		T11	414
valid_sources[0x28]	3564	1			T6	178		T11	235		T69	1
valid_sources[0x29]	3645	1			T6	161		T11	302		T69	1
valid_sources[0x2a]	3395	1			T6	156		T11	208		T123	1
valid_sources[0x2b]	3997	1			T6	157		T11	294		T29	3
valid_sources[0x2c]	3617	1			T4	1		T6	165		T11	399
valid_sources[0x2d]	3622	1			T6	185		T11	244		T69	1
valid_sources[0x2e]	3993	1			T6	183		T11	319		T84	2
valid_sources[0x2f]	3755	1			T6	162		T11	246		T84	1
valid_sources[0x30]	3478	1			T6	155		T11	318		T67	1
valid_sources[0x31]	3526	1			T4	1		T6	172		T11	341
valid_sources[0x32]	4003	1			T6	174		T11	370		T123	4
valid_sources[0x33]	3636	1			T6	175		T11	117		T67	1
valid_sources[0x34]	3627	1			T6	186		T15	4		T11	363
valid_sources[0x35]	3802	1			T6	182		T11	102		T68	2
valid_sources[0x36]	3473	1			T6	176		T11	189		T69	1
valid_sources[0x37]	3266	1			T6	167		T11	190		T68	1
valid_sources[0x38]	3792	1			T6	153		T11	490		T120	1
valid_sources[0x39]	4040	1			T6	176		T13	3		T11	245
valid_sources[0x3a]	3577	1			T6	199		T11	195		T29	2
valid_sources[0x3b]	3399	1			T1	1		T6	188		T11	257
valid_sources[0x3c]	3406	1			T6	192		T11	332		T66	1
valid_sources[0x3d]	3426	1			T6	174		T11	36		T96	3
valid_sources[0x3e]	3464	1			T6	192		T11	130		T66	1
valid_sources[0x3f]	3198	1			T6	149		T11	214		T118	3
valid_sources[0x40]	3544	1			T6	179		T11	287		T67	1
valid_sources[0x41]	4255	1			T6	152		T13	2		T11	238
valid_sources[0x42]	3757	1			T6	165		T11	111		T66	1
valid_sources[0x43]	3638	1			T6	179		T11	218		T27	1
valid_sources[0x44]	3602	1			T6	185		T11	366		T68	2
valid_sources[0x45]	3737	1			T4	1		T6	197		T11	197
valid_sources[0x46]	3903	1			T6	147		T11	314		T69	1
valid_sources[0x47]	3915	1			T6	177		T11	605		T96	8
valid_sources[0x48]	3394	1			T6	162		T11	256		T116	1
valid_sources[0x49]	4038	1			T6	166		T11	207		T67	2
valid_sources[0x4a]	3596	1			T6	177		T11	251		T121	1
valid_sources[0x4b]	3788	1			T6	178		T11	370		T120	1
valid_sources[0x4c]	3322	1			T6	155		T13	1		T11	287
valid_sources[0x4d]	4090	1			T6	190		T11	234		T64	6
valid_sources[0x4e]	3518	1			T6	156		T11	267		T118	1
valid_sources[0x4f]	3387	1			T6	174		T11	184		T27	1
valid_sources[0x50]	3843	1			T6	194		T11	309		T30	1
valid_sources[0x51]	3913	1			T6	161		T11	337		T84	1
valid_sources[0x52]	4036	1			T6	173		T14	32		T11	270
valid_sources[0x53]	3589	1			T6	160		T11	276		T18	4
valid_sources[0x54]	3506	1			T6	164		T11	402		T24	1
valid_sources[0x55]	3581	1			T6	172		T8	2		T11	131
valid_sources[0x56]	3659	1			T6	185		T11	218		T67	6
valid_sources[0x57]	4044	1			T6	167		T13	1		T11	262
valid_sources[0x58]	3689	1			T6	171		T11	220		T122	1
valid_sources[0x59]	3399	1			T6	176		T11	321		T115	5
valid_sources[0x5a]	3581	1			T6	160		T11	278		T29	7
valid_sources[0x5b]	3935	1			T6	152		T13	4		T11	409
valid_sources[0x5c]	3855	1			T6	149		T11	227		T27	1
valid_sources[0x5d]	3478	1			T6	173		T11	94		T122	1
valid_sources[0x5e]	3016	1			T6	179		T11	202		T53	3
valid_sources[0x5f]	3726	1			T6	178		T11	232		T124	1
valid_sources[0x60]	3421	1			T2	1		T6	164		T11	237
valid_sources[0x61]	3941	1			T6	174		T11	357		T64	1
valid_sources[0x62]	3982	1			T6	159		T11	146		T64	5
valid_sources[0x63]	3809	1			T6	189		T13	1		T11	398
valid_sources[0x64]	3729	1			T6	186		T11	568		T123	3
valid_sources[0x65]	3499	1			T6	168		T11	229		T50	1
valid_sources[0x66]	3799	1			T6	158		T8	1		T11	257
valid_sources[0x67]	3569	1			T6	171		T9	9		T11	195
valid_sources[0x68]	3858	1			T6	166		T11	256		T66	1
valid_sources[0x69]	4050	1			T6	169		T11	448		T120	1
valid_sources[0x6a]	3558	1			T6	151		T13	1		T11	277
valid_sources[0x6b]	3512	1			T6	191		T11	227		T116	1
valid_sources[0x6c]	3773	1			T6	168		T11	495		T120	1
valid_sources[0x6d]	3809	1			T6	163		T13	1		T11	210
valid_sources[0x6e]	3811	1			T6	169		T11	167		T49	9
valid_sources[0x6f]	3335	1			T6	160		T13	4		T11	205
valid_sources[0x70]	3818	1			T6	170		T11	170		T27	1
valid_sources[0x71]	3500	1			T6	166		T17	1		T11	235
valid_sources[0x72]	3455	1			T6	160		T11	270		T84	1
valid_sources[0x73]	3887	1			T6	178		T11	274		T27	1
valid_sources[0x74]	3155	1			T6	162		T13	1		T11	111
valid_sources[0x75]	3933	1			T6	184		T13	1		T11	417
valid_sources[0x76]	3774	1			T6	180		T11	233		T124	2
valid_sources[0x77]	3711	1			T6	182		T11	403		T22	186
valid_sources[0x78]	3598	1			T6	187		T17	1		T11	193
valid_sources[0x79]	3550	1			T6	187		T8	6		T11	190
valid_sources[0x7a]	3574	1			T6	144		T11	147		T84	1
valid_sources[0x7b]	3677	1			T6	157		T11	210		T120	1
valid_sources[0x7c]	3820	1			T6	171		T11	328		T18	1
valid_sources[0x7d]	3980	1			T6	161		T11	394		T22	389
valid_sources[0x7e]	3344	1			T6	160		T11	125		T22	36
valid_sources[0x7f]	3605	1			T6	190		T11	129		T66	1
valid_sources[0x80]	3723	1			T6	165		T8	1		T11	249

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

217856

1

T3

9

T6

10169

T7

10

values[0x0]

all_enables

biggest_size

320422

1

T1

1

T6

15073

T17

1

values[0x1]

all_enables

biggest_size

318979

1

T6

14775

T11

23386

T49

1