Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2059755

1

T5

277

T6

99491

T7

58

full_word

1307946

1

T3

4

T5

37

T6

60762

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3367391	1			T3	4		T5	314		T6	160253
auto[TlIntgErrCmd]	105	1			T44	6		T45	4		T46	8
auto[TlIntgErrData]	103	1			T44	3		T45	8		T46	9
auto[TlIntgErrBoth]	102	1			T44	1		T45	8		T46	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

544542

1

T3

4

T5

314

T6

25080

auto[1]

2823159

1

T6

135173

T11

201519

T22

121913

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	234747	1			T5	277		T6	10685		T7	58
auto[TlIntgErrNone]	partial	auto[1]	1824727	1			T6	88806		T11	128279		T22	80565
auto[TlIntgErrNone]	full_word	auto[0]	309665	1			T3	4		T5	37		T6	14395
auto[TlIntgErrNone]	full_word	auto[1]	998252	1			T6	46367		T11	73240		T22	41348
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T44	2		T45	1		T46	3
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T44	3		T45	2		T46	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T46	1		T99	1		T104	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T44	1		T45	1		T102	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T44	2		T45	4		T46	5
auto[TlIntgErrData]	partial	auto[1]	52	1			T45	4		T46	4		T97	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T106	1		T107	2		T108	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T44	1		T97	1		T109	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T44	1		T45	2		T46	1
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T45	6		T46	2		T97	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T102	1		T101	1		T110	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T98	1		T104	1		T108	1