Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3187309

1

T4

347

T5

53

T6

344

full_word

2046884

1

T2

6

T4

36

T5

7

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	5233873	1			T2	6		T4	383		T5	60
auto[TlIntgErrCmd]	109	1			T59	4		T60	4		T61	6
auto[TlIntgErrData]	99	1			T59	7		T60	6		T61	10
auto[TlIntgErrBoth]	112	1			T59	9		T60	10		T61	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

828246

1

T2

6

T4

383

T5

60

auto[1]

4405947

1

T12

188061

T14

111606

T15

155012

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	343674	1			T4	347		T5	53		T6	344
auto[TlIntgErrNone]	partial	auto[1]	2843338	1			T12	119574		T14	719554		T15	101750
auto[TlIntgErrNone]	full_word	auto[0]	484422	1			T2	6		T4	36		T5	7
auto[TlIntgErrNone]	full_word	auto[1]	1562439	1			T12	68487		T14	396506		T15	53262
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T59	3		T60	2		T61	3
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T60	2		T61	3		T102	3
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T59	1		T106	1		T107	2
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T102	1		T104	1		T105	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T59	4		T60	4		T61	3
auto[TlIntgErrData]	partial	auto[1]	46	1			T59	3		T60	2		T61	7
auto[TlIntgErrData]	full_word	auto[0]	3	1			T108	1		T100	1		T109	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T101	1		T110	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T60	6		T61	2		T102	2
auto[TlIntgErrBoth]	partial	auto[1]	64	1			T59	6		T60	4		T61	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T59	1		T61	1		T108	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T59	2		T109	1		-	-