Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2484458

1

T1

64

T2

50

T3

88

full_word

1578357

1

T1

4

T2

5

T3

9

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4062495	1			T1	68		T2	55		T3	97
auto[TlIntgErrCmd]	113	1			T53	6		T54	1		T55	4
auto[TlIntgErrData]	106	1			T53	11		T54	6		T101	3
auto[TlIntgErrBoth]	101	1			T53	3		T54	3		T55	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

648386

1

T1

68

T2

55

T3

97

auto[1]

3414429

1

T11

296741

T13

279044

T14

267111

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	275010	1			T1	64		T2	50		T3	88
auto[TlIntgErrNone]	partial	auto[1]	2209148	1			T11	191009		T13	179112		T14	176557
auto[TlIntgErrNone]	full_word	auto[0]	373240	1			T1	4		T2	5		T3	9
auto[TlIntgErrNone]	full_word	auto[1]	1205097	1			T11	105732		T13	99932		T14	90554
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T53	3		T55	1		T101	2
auto[TlIntgErrCmd]	partial	auto[1]	72	1			T53	3		T55	3		T101	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T110	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T54	1		T105	1		T111	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T53	3		T54	3		T102	4
auto[TlIntgErrData]	partial	auto[1]	53	1			T53	8		T54	3		T101	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T101	1		T110	1		T107	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T112	2		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T53	2		T54	1		T55	3
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T53	1		T54	2		T55	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T103	1		T106	1		T111	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T55	2		T107	1		T108	1