Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

930418

1

T3

63

T6

68

T8

44

full_word

580474

1

T3

3

T5

4

T6

3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1510602	1			T3	66		T5	4		T6	71
auto[TlIntgErrCmd]	88	1			T54	2		T55	8		T56	7
auto[TlIntgErrData]	99	1			T54	2		T55	8		T56	9
auto[TlIntgErrBoth]	103	1			T54	6		T55	4		T56	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

255457

1

T3

66

T5

4

T6

71

auto[1]

1255435

1

T14

14314

T15

329600

T16

142585

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	116646	1			T3	63		T6	68		T8	44
auto[TlIntgErrNone]	partial	auto[1]	813506	1			T14	9311		T15	210170		T16	92769
auto[TlIntgErrNone]	full_word	auto[0]	138679	1			T3	3		T5	4		T6	3
auto[TlIntgErrNone]	full_word	auto[1]	441771	1			T14	5003		T15	119430		T16	49816
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T54	1		T55	2		T56	4
auto[TlIntgErrCmd]	partial	auto[1]	42	1			T54	1		T55	6		T56	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T104	1		T107	1		T103	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T56	1		T108	1		T109	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T54	1		T55	3		T56	5
auto[TlIntgErrData]	partial	auto[1]	49	1			T54	1		T55	4		T56	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T56	1		T110	1		T111	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T55	1		T103	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T54	1		T55	1		T56	1
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T54	4		T55	3		T56	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T104	1		T112	1		T109	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T54	1		T113	1		T104	1