Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1370379

1

T1

92581

T2

62

T3

54

full_word

847253

1

T1

57207

T2

4

T3

7

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2217372	1			T1	149788		T2	66		T3	61
auto[TlIntgErrCmd]	86	1			T60	7		T62	4		T63	6
auto[TlIntgErrData]	92	1			T60	5		T62	5		T63	7
auto[TlIntgErrBoth]	82	1			T60	8		T62	1		T63	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

360647

1

T1

22955

T2

66

T3

61

auto[1]

1856985

1

T1

126833

T11

217940

T12

525078

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	159849	1			T1	9437		T2	62		T3	54
auto[TlIntgErrNone]	partial	auto[1]	1210298	1			T1	83144		T11	140038		T12	342216
auto[TlIntgErrNone]	full_word	auto[0]	200679	1			T1	13518		T2	4		T3	7
auto[TlIntgErrNone]	full_word	auto[1]	646546	1			T1	43689		T11	77902		T12	182862
auto[TlIntgErrCmd]	partial	auto[0]	27	1			T60	3		T62	1		T63	2
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T60	4		T62	3		T63	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T119	1		T113	1		T120	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T63	1		T119	1		T115	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T60	2		T62	2		T63	4
auto[TlIntgErrData]	partial	auto[1]	31	1			T60	3		T62	3		T63	3
auto[TlIntgErrData]	full_word	auto[0]	7	1			T121	1		T113	3		T117	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T113	1		T120	2		T114	1
auto[TlIntgErrBoth]	partial	auto[0]	28	1			T60	4		T62	1		T63	1
auto[TlIntgErrBoth]	partial	auto[1]	43	1			T60	2		T63	5		T118	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T60	1		T63	1		T121	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T60	1		T118	1		T116	1