Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1856385

1

T1

78

T4

65

T5

211

full_word

1173866

1

T1

11

T3

6

T4

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3029951	1			T1	89		T3	6		T4	69
auto[TlIntgErrCmd]	100	1			T54	4		T55	5		T56	7
auto[TlIntgErrData]	85	1			T54	2		T55	6		T56	9
auto[TlIntgErrBoth]	115	1			T54	4		T55	9		T56	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

491297

1

T1

89

T3

6

T4

69

auto[1]

2538954

1

T14

115169

T15

246476

T16

132034

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	213133	1			T1	78		T4	65		T5	211
auto[TlIntgErrNone]	partial	auto[1]	1642975	1			T14	73430		T15	161972		T16	85523
auto[TlIntgErrNone]	full_word	auto[0]	278036	1			T1	11		T3	6		T4	4
auto[TlIntgErrNone]	full_word	auto[1]	895807	1			T14	41739		T15	84504		T16	46511
auto[TlIntgErrCmd]	partial	auto[0]	32	1			T54	2		T55	1		T56	2
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T54	2		T55	3		T56	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T55	1		T56	2		T102	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T103	1		T104	1		T102	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T55	6		T56	3		T99	1
auto[TlIntgErrData]	partial	auto[1]	37	1			T54	2		T56	6		T99	2
auto[TlIntgErrData]	full_word	auto[0]	2	1			T101	1		T105	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1			T99	1		T100	1		T102	1
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T54	1		T55	5		T56	1
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T54	3		T55	3		T56	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T55	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T99	1		T106	1		T107	3