Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	38991	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

605457

1

T1

25

T3

10

T5

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	179736	1			T1	191		T3	114		T5	6
values[0x0]	228580	1			T14	45957		T15	16386		T16	98715
values[0x1]	236132	1			T14	47585		T15	16927		T16	102156

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	19084	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

625364

1

T1

108

T3

74

T5

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2393	1			T10	6		T50	6		T137	1
valid_sources[0x01]	3431	1			T10	6		T138	1		T88	1
valid_sources[0x02]	2322	1			T139	6		T14	484		T140	7
valid_sources[0x03]	2484	1			T10	3		T18	2		T138	3
valid_sources[0x04]	3594	1			T6	4		T8	1		T13	2
valid_sources[0x05]	2352	1			T20	2		T12	1		T138	2
valid_sources[0x06]	2383	1			T1	6		T6	4		T138	1
valid_sources[0x07]	2918	1			T20	2		T138	1		T88	3
valid_sources[0x08]	2356	1			T20	1		T138	2		T88	4
valid_sources[0x09]	2345	1			T1	6		T8	1		T138	1
valid_sources[0x0a]	2656	1			T1	2		T10	18		T20	1
valid_sources[0x0b]	2753	1			T137	1		T139	1		T14	456
valid_sources[0x0c]	2318	1			T11	1		T19	8		T138	1
valid_sources[0x0d]	2513	1			T3	1		T6	2		T139	5
valid_sources[0x0e]	2815	1			T1	1		T3	5		T6	7
valid_sources[0x0f]	2481	1			T19	4		T138	1		T141	1
valid_sources[0x10]	2575	1			T3	1		T8	1		T20	2
valid_sources[0x11]	2436	1			T88	2		T137	1		T139	1
valid_sources[0x12]	3593	1			T138	2		T88	5		T137	1
valid_sources[0x13]	2177	1			T8	2		T11	1		T44	11
valid_sources[0x14]	3021	1			T6	2		T10	21		T138	1
valid_sources[0x15]	2245	1			T6	4		T18	1		T137	1
valid_sources[0x16]	2467	1			T3	7		T10	11		T12	1
valid_sources[0x17]	2366	1			T10	4		T88	3		T137	1
valid_sources[0x18]	2457	1			T6	1		T10	1		T20	1
valid_sources[0x19]	2277	1			T138	1		T137	1		T141	3
valid_sources[0x1a]	2681	1			T19	3		T138	1		T139	3
valid_sources[0x1b]	2190	1			T138	2		T137	2		T139	4
valid_sources[0x1c]	2490	1			T3	2		T6	6		T137	2
valid_sources[0x1d]	2275	1			T1	6		T137	3		T142	23
valid_sources[0x1e]	2403	1			T1	7		T6	1		T19	1
valid_sources[0x1f]	2578	1			T8	1		T137	1		T141	3
valid_sources[0x20]	2318	1			T3	4		T8	1		T10	1
valid_sources[0x21]	2451	1			T18	6		T20	1		T138	2
valid_sources[0x22]	2310	1			T1	1		T8	1		T19	2
valid_sources[0x23]	2375	1			T8	1		T20	1		T138	1
valid_sources[0x24]	2277	1			T3	1		T8	1		T18	7
valid_sources[0x25]	2363	1			T8	1		T10	3		T19	1
valid_sources[0x26]	2356	1			T1	7		T8	1		T21	1
valid_sources[0x27]	2647	1			T138	2		T137	1		T141	1
valid_sources[0x28]	2360	1			T6	4		T12	1		T138	3
valid_sources[0x29]	2954	1			T1	12		T3	17		T6	2
valid_sources[0x2a]	2684	1			T11	1		T13	1		T138	2
valid_sources[0x2b]	2681	1			T11	2		T12	2		T137	3
valid_sources[0x2c]	2498	1			T6	3		T8	2		T88	1
valid_sources[0x2d]	2279	1			T141	2		T14	423		T64	3
valid_sources[0x2e]	2353	1			T11	1		T138	1		T137	1
valid_sources[0x2f]	2340	1			T6	1		T12	1		T137	1
valid_sources[0x30]	2290	1			T19	1		T137	2		T139	10
valid_sources[0x31]	2395	1			T141	3		T14	448		T35	1
valid_sources[0x32]	2345	1			T19	2		T12	3		T138	2
valid_sources[0x33]	2395	1			T88	4		T137	4		T141	5
valid_sources[0x34]	2449	1			T139	6		T14	435		T64	1
valid_sources[0x35]	2426	1			T10	3		T18	1		T88	8
valid_sources[0x36]	2587	1			T5	6		T10	3		T138	1
valid_sources[0x37]	2864	1			T8	1		T19	2		T141	1
valid_sources[0x38]	2184	1			T1	1		T10	9		T11	2
valid_sources[0x39]	2646	1			T12	1		T138	1		T137	2
valid_sources[0x3a]	2384	1			T19	2		T20	1		T12	1
valid_sources[0x3b]	2320	1			T3	2		T8	1		T12	1
valid_sources[0x3c]	2559	1			T1	11		T6	10		T10	4
valid_sources[0x3d]	2324	1			T6	1		T46	14		T138	1
valid_sources[0x3e]	2304	1			T8	1		T18	3		T21	2
valid_sources[0x3f]	2284	1			T8	1		T138	1		T137	2
valid_sources[0x40]	3155	1			T137	2		T141	1		T14	490
valid_sources[0x41]	2296	1			T8	1		T20	1		T139	5
valid_sources[0x42]	2296	1			T3	2		T20	1		T12	2
valid_sources[0x43]	2527	1			T8	1		T11	3		T19	1
valid_sources[0x44]	2688	1			T11	5		T12	1		T138	1
valid_sources[0x45]	2490	1			T3	1		T19	6		T12	1
valid_sources[0x46]	2477	1			T19	1		T137	1		T139	1
valid_sources[0x47]	2396	1			T12	1		T141	1		T14	480
valid_sources[0x48]	2429	1			T19	1		T20	2		T138	1
valid_sources[0x49]	2585	1			T10	3		T19	2		T20	1
valid_sources[0x4a]	2293	1			T1	5		T19	1		T141	1
valid_sources[0x4b]	2360	1			T20	2		T88	2		T141	1
valid_sources[0x4c]	2434	1			T138	1		T141	2		T14	455
valid_sources[0x4d]	2898	1			T19	2		T138	1		T137	1
valid_sources[0x4e]	4113	1			T20	2		T138	1		T143	22
valid_sources[0x4f]	2416	1			T12	1		T138	1		T137	1
valid_sources[0x50]	2572	1			T1	2		T3	1		T6	4
valid_sources[0x51]	2304	1			T1	1		T11	1		T19	1
valid_sources[0x52]	2369	1			T138	1		T137	1		T14	519
valid_sources[0x53]	2754	1			T6	1		T12	1		T50	3
valid_sources[0x54]	2296	1			T10	2		T50	3		T14	475
valid_sources[0x55]	2649	1			T138	2		T137	1		T38	1
valid_sources[0x56]	2371	1			T138	1		T137	2		T141	1
valid_sources[0x57]	2796	1			T20	1		T138	2		T137	1
valid_sources[0x58]	2519	1			T12	2		T137	2		T143	40
valid_sources[0x59]	2344	1			T6	2		T8	2		T10	5
valid_sources[0x5a]	2301	1			T3	2		T11	1		T19	4
valid_sources[0x5b]	2461	1			T88	1		T137	2		T139	2
valid_sources[0x5c]	2233	1			T1	2		T138	1		T137	1
valid_sources[0x5d]	3047	1			T1	6		T10	3		T20	1
valid_sources[0x5e]	2552	1			T8	2		T20	2		T88	4
valid_sources[0x5f]	2363	1			T8	1		T137	2		T141	2
valid_sources[0x60]	2585	1			T6	2		T10	2		T18	6
valid_sources[0x61]	2434	1			T1	8		T138	1		T137	1
valid_sources[0x62]	3238	1			T10	1		T12	1		T88	10
valid_sources[0x63]	2307	1			T3	4		T138	2		T137	1
valid_sources[0x64]	2508	1			T12	1		T138	1		T88	3
valid_sources[0x65]	2400	1			T6	2		T8	2		T138	1
valid_sources[0x66]	2333	1			T10	3		T20	2		T138	1
valid_sources[0x67]	2817	1			T19	1		T137	1		T141	2
valid_sources[0x68]	2573	1			T8	1		T20	1		T138	1
valid_sources[0x69]	2253	1			T3	4		T18	3		T11	2
valid_sources[0x6a]	2334	1			T8	1		T10	5		T138	1
valid_sources[0x6b]	2444	1			T139	1		T144	21		T141	1
valid_sources[0x6c]	2597	1			T1	13		T6	1		T12	1
valid_sources[0x6d]	3051	1			T6	3		T19	4		T12	1
valid_sources[0x6e]	2414	1			T19	5		T137	1		T38	1
valid_sources[0x6f]	2412	1			T138	1		T139	9		T141	2
valid_sources[0x70]	2268	1			T138	5		T137	1		T141	2
valid_sources[0x71]	2368	1			T8	1		T18	3		T19	2
valid_sources[0x72]	2694	1			T1	14		T8	1		T20	1
valid_sources[0x73]	3044	1			T1	5		T3	4		T10	4
valid_sources[0x74]	2434	1			T3	2		T11	6		T19	2
valid_sources[0x75]	2283	1			T10	2		T18	3		T11	1
valid_sources[0x76]	2693	1			T1	4		T12	1		T46	30
valid_sources[0x77]	2429	1			T3	5		T10	15		T19	1
valid_sources[0x78]	2277	1			T8	3		T11	1		T20	2
valid_sources[0x79]	2195	1			T1	2		T8	1		T18	1
valid_sources[0x7a]	2255	1			T19	1		T12	1		T138	1
valid_sources[0x7b]	2388	1			T20	2		T137	3		T141	2
valid_sources[0x7c]	2365	1			T138	1		T137	1		T141	1
valid_sources[0x7d]	2347	1			T19	2		T12	1		T137	1
valid_sources[0x7e]	2384	1			T8	1		T19	1		T138	3
valid_sources[0x7f]	2334	1			T3	5		T138	1		T137	2
valid_sources[0x80]	2369	1			T8	1		T10	3		T11	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

153011

1

T1

25

T3

10

T5

6

values[0x0]

all_enables

biggest_size

226580

1

T14

45568

T15

16263

T16

97823

values[0x1]

all_enables

biggest_size

225866

1

T14

45583

T15

16247

T16

97629

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	50866	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

480029

1

T1

46

T2

5

T5

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	136393	1			T1	96		T4	1		T5	23
values[0x0]	183789	1			T2	4		T9	5		T25	7
values[0x1]	210713	1			T2	5		T9	5		T25	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	24527	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

506368

1

T1

55

T2

5

T4

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1841	1			T14	395		T145	10		T146	1
valid_sources[0x01]	1667	1			T88	1		T144	1		T14	374
valid_sources[0x02]	1935	1			T14	425		T89	2		T147	1
valid_sources[0x03]	1846	1			T1	1		T20	1		T14	357
valid_sources[0x04]	1859	1			T50	1		T88	1		T144	2
valid_sources[0x05]	2328	1			T20	1		T21	13		T48	1
valid_sources[0x06]	1993	1			T8	3		T49	1		T144	1
valid_sources[0x07]	2140	1			T14	427		T148	9		T149	1
valid_sources[0x08]	2392	1			T1	2		T88	2		T150	1
valid_sources[0x09]	2000	1			T88	3		T150	1		T14	377
valid_sources[0x0a]	2467	1			T1	3		T49	1		T88	2
valid_sources[0x0b]	1907	1			T49	2		T50	1		T88	1
valid_sources[0x0c]	1525	1			T50	1		T150	1		T14	326
valid_sources[0x0d]	2054	1			T14	412		T40	3		T151	1
valid_sources[0x0e]	1958	1			T48	1		T49	1		T14	408
valid_sources[0x0f]	2078	1			T88	2		T14	395		T32	1
valid_sources[0x10]	1917	1			T48	1		T150	1		T14	398
valid_sources[0x11]	1651	1			T18	2		T14	366		T31	1
valid_sources[0x12]	2373	1			T1	2		T5	2		T14	405
valid_sources[0x13]	1935	1			T5	1		T8	1		T20	2
valid_sources[0x14]	2347	1			T49	1		T14	349		T147	1
valid_sources[0x15]	2453	1			T14	304		T39	2		T32	1
valid_sources[0x16]	1810	1			T14	379		T39	1		T152	1
valid_sources[0x17]	2820	1			T88	1		T14	414		T15	168
valid_sources[0x18]	1902	1			T20	1		T49	2		T14	327
valid_sources[0x19]	2361	1			T49	1		T14	420		T153	1
valid_sources[0x1a]	2220	1			T1	1		T88	1		T14	371
valid_sources[0x1b]	1807	1			T14	363		T36	1		T154	2
valid_sources[0x1c]	2115	1			T5	1		T8	1		T50	1
valid_sources[0x1d]	2871	1			T1	1		T14	343		T15	152
valid_sources[0x1e]	2089	1			T48	1		T14	417		T145	2
valid_sources[0x1f]	2028	1			T88	3		T14	357		T145	5
valid_sources[0x20]	1873	1			T4	1		T48	1		T14	453
valid_sources[0x21]	2395	1			T20	5		T48	1		T14	427
valid_sources[0x22]	1775	1			T48	1		T14	421		T39	4
valid_sources[0x23]	2235	1			T1	1		T8	3		T14	404
valid_sources[0x24]	2079	1			T5	4		T14	402		T155	2
valid_sources[0x25]	1664	1			T88	1		T144	5		T14	404
valid_sources[0x26]	1605	1			T18	3		T144	1		T14	408
valid_sources[0x27]	1680	1			T88	2		T150	1		T14	354
valid_sources[0x28]	1928	1			T48	1		T144	2		T14	335
valid_sources[0x29]	1745	1			T50	1		T150	2		T14	345
valid_sources[0x2a]	1777	1			T1	1		T20	1		T14	369
valid_sources[0x2b]	1479	1			T13	30		T14	401		T89	5
valid_sources[0x2c]	2104	1			T1	2		T88	1		T14	352
valid_sources[0x2d]	2095	1			T48	1		T14	382		T39	1
valid_sources[0x2e]	2106	1			T1	2		T76	3		T14	409
valid_sources[0x2f]	2297	1			T1	3		T2	1		T8	1
valid_sources[0x30]	2127	1			T50	1		T88	2		T14	391
valid_sources[0x31]	1868	1			T14	403		T22	1		T29	1
valid_sources[0x32]	1795	1			T1	3		T14	419		T15	149
valid_sources[0x33]	2401	1			T20	1		T25	18		T14	383
valid_sources[0x34]	2359	1			T48	2		T14	391		T156	1
valid_sources[0x35]	2505	1			T14	373		T156	1		T32	1
valid_sources[0x36]	2230	1			T1	1		T8	1		T14	373
valid_sources[0x37]	1800	1			T1	1		T18	5		T14	398
valid_sources[0x38]	1767	1			T1	5		T14	349		T157	1
valid_sources[0x39]	1957	1			T14	390		T155	2		T15	161
valid_sources[0x3a]	1951	1			T50	1		T14	392		T158	1
valid_sources[0x3b]	2862	1			T1	2		T150	1		T14	417
valid_sources[0x3c]	1939	1			T1	4		T14	390		T156	1
valid_sources[0x3d]	1804	1			T20	1		T14	332		T155	1
valid_sources[0x3e]	2083	1			T1	1		T14	318		T148	7
valid_sources[0x3f]	1691	1			T1	2		T2	1		T14	373
valid_sources[0x40]	2155	1			T20	1		T14	428		T156	1
valid_sources[0x41]	2263	1			T75	1		T14	338		T159	1
valid_sources[0x42]	2012	1			T88	1		T14	400		T149	1
valid_sources[0x43]	1813	1			T14	357		T154	2		T146	1
valid_sources[0x44]	2514	1			T8	2		T20	1		T88	4
valid_sources[0x45]	2663	1			T50	1		T14	380		T160	34
valid_sources[0x46]	1680	1			T14	387		T32	1		T161	1
valid_sources[0x47]	2317	1			T1	2		T14	351		T89	5
valid_sources[0x48]	2375	1			T14	423		T154	2		T152	2
valid_sources[0x49]	1981	1			T88	1		T14	373		T151	1
valid_sources[0x4a]	2337	1			T137	128		T14	415		T156	1
valid_sources[0x4b]	2146	1			T88	1		T14	378		T29	4
valid_sources[0x4c]	2196	1			T144	4		T14	367		T162	5
valid_sources[0x4d]	1644	1			T1	1		T8	1		T88	1
valid_sources[0x4e]	1980	1			T163	1		T14	368		T32	1
valid_sources[0x4f]	2161	1			T50	1		T14	394		T89	1
valid_sources[0x50]	1914	1			T5	2		T14	327		T146	1
valid_sources[0x51]	2182	1			T1	2		T48	1		T50	1
valid_sources[0x52]	1959	1			T50	2		T14	381		T31	1
valid_sources[0x53]	2293	1			T1	1		T14	381		T155	1
valid_sources[0x54]	2232	1			T1	1		T14	391		T157	1
valid_sources[0x55]	2325	1			T8	1		T9	10		T48	1
valid_sources[0x56]	2695	1			T48	1		T14	380		T40	3
valid_sources[0x57]	2184	1			T50	1		T14	385		T154	1
valid_sources[0x58]	1741	1			T1	1		T14	390		T152	1
valid_sources[0x59]	2344	1			T5	2		T20	1		T14	420
valid_sources[0x5a]	2841	1			T48	1		T14	336		T162	3
valid_sources[0x5b]	3263	1			T18	10		T14	332		T154	1
valid_sources[0x5c]	2730	1			T14	389		T40	1		T36	1
valid_sources[0x5d]	1727	1			T8	1		T20	1		T88	1
valid_sources[0x5e]	2554	1			T1	1		T20	1		T14	395
valid_sources[0x5f]	1860	1			T14	394		T43	1		T164	1
valid_sources[0x60]	2294	1			T14	420		T162	2		T43	1
valid_sources[0x61]	1916	1			T88	1		T14	369		T164	2
valid_sources[0x62]	1845	1			T1	2		T14	376		T151	2
valid_sources[0x63]	1772	1			T14	338		T149	1		T165	1
valid_sources[0x64]	2307	1			T88	1		T150	1		T14	384
valid_sources[0x65]	1851	1			T8	1		T50	1		T14	414
valid_sources[0x66]	1717	1			T2	3		T88	1		T14	438
valid_sources[0x67]	1842	1			T8	1		T144	1		T14	352
valid_sources[0x68]	1805	1			T20	1		T50	1		T88	2
valid_sources[0x69]	1812	1			T88	2		T14	376		T161	2
valid_sources[0x6a]	1633	1			T1	1		T48	1		T14	376
valid_sources[0x6b]	1701	1			T8	1		T14	394		T166	1
valid_sources[0x6c]	1356	1			T1	2		T14	371		T51	1
valid_sources[0x6d]	1884	1			T14	346		T89	5		T154	1
valid_sources[0x6e]	1642	1			T8	1		T20	1		T144	1
valid_sources[0x6f]	2134	1			T14	395		T146	2		T167	2
valid_sources[0x70]	2374	1			T14	428		T155	1		T15	122
valid_sources[0x71]	2365	1			T8	1		T150	1		T14	356
valid_sources[0x72]	1914	1			T88	1		T14	417		T157	1
valid_sources[0x73]	2128	1			T50	1		T73	13		T14	458
valid_sources[0x74]	2095	1			T48	1		T52	1		T14	394
valid_sources[0x75]	1883	1			T1	1		T45	1		T144	1
valid_sources[0x76]	2374	1			T14	398		T168	1		T151	1
valid_sources[0x77]	1917	1			T8	2		T48	2		T14	391
valid_sources[0x78]	2368	1			T14	337		T155	1		T164	2
valid_sources[0x79]	2073	1			T14	436		T42	9		T15	166
valid_sources[0x7a]	1985	1			T88	3		T14	408		T164	1
valid_sources[0x7b]	2054	1			T14	403		T32	2		T15	146
valid_sources[0x7c]	1941	1			T88	1		T14	368		T162	1
valid_sources[0x7d]	2396	1			T14	423		T15	166		T169	1
valid_sources[0x7e]	1805	1			T14	467		T164	1		T15	153
valid_sources[0x7f]	2603	1			T14	330		T164	1		T15	168
valid_sources[0x80]	1713	1			T74	2		T14	419		T29	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

122190

1

T1

46

T5

17

T6

27

values[0x0]

all_enables

biggest_size

179631

1

T2

3

T9

3

T25

3

values[0x1]

all_enables

biggest_size

178208

1

T2

2

T9

1

T25

3