Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1106770

1

T1

166

T3

104

T6

142

full_word

705310

1

T1

25

T3

10

T5

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1811790	1			T1	191		T3	114		T5	4
auto[TlIntgErrCmd]	98	1			T60	5		T69	5		T70	2
auto[TlIntgErrData]	92	1			T60	9		T69	4		T70	4
auto[TlIntgErrBoth]	100	1			T60	6		T69	1		T70	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300854

1

T1

191

T3

114

T5

4

auto[1]

1511226

1

T14

295984

T15

107753

T16

673675

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	133368	1			T1	166		T3	104		T6	142
auto[TlIntgErrNone]	partial	auto[1]	973133	1			T14	188443		T15	69223		T16	439532
auto[TlIntgErrNone]	full_word	auto[0]	167364	1			T1	25		T3	10		T5	4
auto[TlIntgErrNone]	full_word	auto[1]	537925	1			T14	107541		T15	38530		T16	234143
auto[TlIntgErrCmd]	partial	auto[0]	30	1			T60	3		T69	1		T70	1
auto[TlIntgErrCmd]	partial	auto[1]	62	1			T60	2		T69	4		T70	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T132	2		T127	1		T128	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T124	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	44	1			T60	3		T69	1		T70	1
auto[TlIntgErrData]	partial	auto[1]	41	1			T60	6		T69	3		T70	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T70	1		T133	1		T134	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T70	1		T133	1		T135	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T60	2		T70	3		T123	5
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T60	3		T69	1		T70	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T128	1		T124	1		T125	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T60	1		T128	1		T124	1