Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 31530 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 408183 1 T2 7 T3 6 T4 3



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 127629 1 T2 81 T3 70 T4 3
values[0x0] 153284 1 T14 32424 T15 38598 T16 21085
values[0x1] 158800 1 T14 33515 T15 40384 T16 21803



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 15214 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 424499 1 T2 50 T3 44 T4 3



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 1490 1 T2 1 T8 1 T17 12
valid_sources[0x01] 2044 1 T3 1 T8 1 T129 1
valid_sources[0x02] 1718 1 T6 5 T130 4 T129 2
valid_sources[0x03] 1711 1 T112 5 T89 2 T131 11
valid_sources[0x04] 1659 1 T6 4 T13 5 T113 1
valid_sources[0x05] 1898 1 T8 1 T84 1 T86 1
valid_sources[0x06] 1264 1 T8 6 T11 1 T130 15
valid_sources[0x07] 1487 1 T84 1 T132 1 T89 3
valid_sources[0x08] 1432 1 T8 1 T11 2 T12 1
valid_sources[0x09] 1378 1 T112 1 T85 1 T86 4
valid_sources[0x0a] 1299 1 T12 1 T13 3 T113 2
valid_sources[0x0b] 1645 1 T2 7 T19 6 T113 1
valid_sources[0x0c] 1319 1 T8 1 T11 1 T112 2
valid_sources[0x0d] 1198 1 T8 1 T129 1 T133 1
valid_sources[0x0e] 1864 1 T8 2 T13 4 T113 1
valid_sources[0x0f] 1491 1 T3 3 T8 1 T113 2
valid_sources[0x10] 1858 1 T3 3 T8 3 T11 1
valid_sources[0x11] 1295 1 T8 1 T88 1 T31 2
valid_sources[0x12] 1614 1 T3 1 T8 2 T11 1
valid_sources[0x13] 2017 1 T3 1 T8 2 T11 2
valid_sources[0x14] 1169 1 T3 2 T8 1 T19 2
valid_sources[0x15] 1965 1 T3 1 T6 2 T112 3
valid_sources[0x16] 2597 1 T3 2 T11 1 T13 1
valid_sources[0x17] 1354 1 T8 2 T113 1 T129 2
valid_sources[0x18] 2012 1 T112 2 T86 2 T64 4
valid_sources[0x19] 1950 1 T3 1 T11 1 T84 2
valid_sources[0x1a] 1903 1 T17 6 T11 2 T13 1
valid_sources[0x1b] 1354 1 T6 3 T84 2 T86 1
valid_sources[0x1c] 2238 1 T3 1 T8 4 T17 9
valid_sources[0x1d] 1762 1 T6 9 T8 4 T64 16
valid_sources[0x1e] 1704 1 T112 2 T86 1 T132 1
valid_sources[0x1f] 1990 1 T2 5 T115 37 T132 2
valid_sources[0x20] 1843 1 T8 1 T13 1 T64 2
valid_sources[0x21] 1742 1 T112 5 T129 3 T31 2
valid_sources[0x22] 2537 1 T2 8 T3 1 T8 2
valid_sources[0x23] 1447 1 T8 1 T64 3 T129 1
valid_sources[0x24] 1587 1 T8 1 T129 1 T134 1
valid_sources[0x25] 1485 1 T8 1 T13 1 T86 1
valid_sources[0x26] 1376 1 T6 7 T85 1 T86 1
valid_sources[0x27] 1329 1 T13 5 T112 2 T64 4
valid_sources[0x28] 1518 1 T2 1 T8 1 T113 3
valid_sources[0x29] 1221 1 T11 1 T84 1 T86 1
valid_sources[0x2a] 1247 1 T19 1 T129 3 T135 1
valid_sources[0x2b] 1321 1 T11 2 T13 1 T112 2
valid_sources[0x2c] 1471 1 T3 1 T6 19 T8 1
valid_sources[0x2d] 1584 1 T18 1 T115 31 T136 14
valid_sources[0x2e] 1227 1 T3 2 T8 1 T13 3
valid_sources[0x2f] 1466 1 T8 1 T115 45 T86 1
valid_sources[0x30] 2032 1 T3 1 T13 1 T129 2
valid_sources[0x31] 1952 1 T3 2 T64 10 T133 1
valid_sources[0x32] 1479 1 T8 1 T19 4 T113 1
valid_sources[0x33] 1471 1 T8 3 T137 1 T132 1
valid_sources[0x34] 2024 1 T129 1 T31 2 T138 3
valid_sources[0x35] 1840 1 T3 1 T8 1 T12 1
valid_sources[0x36] 1604 1 T8 1 T85 2 T129 1
valid_sources[0x37] 1334 1 T8 4 T17 2 T13 4
valid_sources[0x38] 1873 1 T3 1 T11 1 T13 4
valid_sources[0x39] 1541 1 T3 1 T8 2 T86 1
valid_sources[0x3a] 1323 1 T8 1 T129 1 T89 3
valid_sources[0x3b] 1922 1 T6 23 T8 2 T112 2
valid_sources[0x3c] 1349 1 T129 1 T132 3 T139 4
valid_sources[0x3d] 2766 1 T8 1 T11 1 T13 2
valid_sources[0x3e] 2304 1 T3 1 T8 2 T12 1
valid_sources[0x3f] 2109 1 T11 1 T12 1 T115 3
valid_sources[0x40] 1617 1 T3 1 T8 2 T39 1
valid_sources[0x41] 1614 1 T11 2 T113 1 T85 14
valid_sources[0x42] 2208 1 T8 1 T129 2 T135 3
valid_sources[0x43] 1379 1 T6 1 T84 1 T113 1
valid_sources[0x44] 1365 1 T86 2 T129 1 T135 1
valid_sources[0x45] 1553 1 T8 1 T13 1 T84 3
valid_sources[0x46] 1408 1 T3 1 T8 1 T13 1
valid_sources[0x47] 2567 1 T8 3 T11 1 T13 1
valid_sources[0x48] 1937 1 T8 2 T85 10 T86 1
valid_sources[0x49] 1958 1 T86 1 T129 1 T137 2
valid_sources[0x4a] 1322 1 T8 1 T12 1 T129 2
valid_sources[0x4b] 1443 1 T129 1 T135 2 T132 2
valid_sources[0x4c] 1299 1 T3 1 T8 1 T13 5
valid_sources[0x4d] 1749 1 T8 4 T129 2 T87 9
valid_sources[0x4e] 1715 1 T12 1 T13 1 T84 1
valid_sources[0x4f] 1652 1 T13 4 T112 2 T113 2
valid_sources[0x50] 1736 1 T64 3 T132 1 T139 2
valid_sources[0x51] 1450 1 T2 1 T18 1 T11 1
valid_sources[0x52] 1766 1 T6 1 T12 1 T13 4
valid_sources[0x53] 2398 1 T19 1 T112 1 T132 4
valid_sources[0x54] 1377 1 T3 1 T8 4 T13 12
valid_sources[0x55] 1476 1 T3 1 T11 2 T13 4
valid_sources[0x56] 1592 1 T84 2 T113 1 T85 3
valid_sources[0x57] 2188 1 T11 1 T84 2 T113 2
valid_sources[0x58] 1795 1 T8 2 T86 3 T89 1
valid_sources[0x59] 1697 1 T8 3 T85 4 T86 2
valid_sources[0x5a] 2407 1 T8 2 T113 4 T115 2
valid_sources[0x5b] 1331 1 T8 5 T13 2 T112 2
valid_sources[0x5c] 1996 1 T8 2 T112 1 T129 1
valid_sources[0x5d] 1925 1 T12 1 T13 4 T112 1
valid_sources[0x5e] 1750 1 T8 1 T13 1 T112 3
valid_sources[0x5f] 2419 1 T3 1 T19 2 T13 1
valid_sources[0x60] 2289 1 T8 2 T129 1 T88 3
valid_sources[0x61] 1442 1 T13 2 T114 14 T137 3
valid_sources[0x62] 1890 1 T19 2 T11 1 T129 1
valid_sources[0x63] 1370 1 T8 4 T11 1 T86 3
valid_sources[0x64] 1666 1 T112 1 T129 1 T132 3
valid_sources[0x65] 3218 1 T3 1 T8 1 T12 2
valid_sources[0x66] 1913 1 T3 1 T84 1 T113 2
valid_sources[0x67] 1976 1 T8 1 T13 4 T129 2
valid_sources[0x68] 1909 1 T8 1 T17 1 T11 1
valid_sources[0x69] 1250 1 T8 1 T19 2 T11 1
valid_sources[0x6a] 1220 1 T12 1 T112 2 T86 2
valid_sources[0x6b] 1390 1 T2 5 T8 1 T10 3
valid_sources[0x6c] 1860 1 T2 7 T64 1 T129 1
valid_sources[0x6d] 2144 1 T64 9 T129 1 T135 1
valid_sources[0x6e] 2253 1 T8 1 T13 7 T112 4
valid_sources[0x6f] 1310 1 T8 2 T12 1 T113 1
valid_sources[0x70] 2017 1 T2 11 T8 2 T11 1
valid_sources[0x71] 2187 1 T11 1 T112 2 T85 15
valid_sources[0x72] 1625 1 T8 1 T13 1 T112 1
valid_sources[0x73] 1255 1 T3 1 T11 2 T84 5
valid_sources[0x74] 1764 1 T13 4 T130 2 T129 2
valid_sources[0x75] 1360 1 T6 7 T8 1 T17 5
valid_sources[0x76] 1638 1 T8 2 T115 9 T129 2
valid_sources[0x77] 2294 1 T8 3 T11 1 T84 2
valid_sources[0x78] 1778 1 T6 2 T8 1 T113 1
valid_sources[0x79] 2211 1 T84 1 T112 2 T130 5
valid_sources[0x7a] 1279 1 T8 1 T84 2 T86 2
valid_sources[0x7b] 1249 1 T11 1 T129 1 T133 1
valid_sources[0x7c] 1367 1 T3 1 T17 4 T84 1
valid_sources[0x7d] 1709 1 T8 1 T135 4 T139 1
valid_sources[0x7e] 1622 1 T3 1 T8 2 T11 1
valid_sources[0x7f] 1425 1 T84 1 T112 1 T132 1
valid_sources[0x80] 1532 1 T3 3 T19 4 T12 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 104443 1 T2 7 T3 6 T4 3
values[0x0] all_enables biggest_size 151917 1 T14 32143 T15 38230 T16 20927
values[0x1] all_enables biggest_size 151823 1 T14 32111 T15 38644 T16 20818


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 35704 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 321343 1 T1 1 T2 18 T3 15



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 93027 1 T1 1 T2 32 T3 32
values[0x0] 122806 1 T5 5 T23 4 T24 8
values[0x1] 141214 1 T5 7 T23 9 T24 3



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 18054 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 338993 1 T1 1 T2 24 T3 19



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 1445 1 T4 5 T114 1 T88 11
valid_sources[0x01] 1387 1 T137 1 T89 1 T90 1
valid_sources[0x02] 1394 1 T12 1 T140 4 T141 1
valid_sources[0x03] 1387 1 T114 2 T39 1 T87 32
valid_sources[0x04] 1477 1 T114 3 T39 1 T85 1
valid_sources[0x05] 1493 1 T85 1 T86 1 T142 1
valid_sources[0x06] 1504 1 T142 1 T30 1 T89 1
valid_sources[0x07] 1352 1 T3 2 T23 3 T143 1
valid_sources[0x08] 1424 1 T1 1 T86 2 T134 1
valid_sources[0x09] 1345 1 T89 2 T144 2 T145 1
valid_sources[0x0a] 1457 1 T137 1 T140 6 T14 251
valid_sources[0x0b] 1476 1 T3 1 T91 1 T146 1
valid_sources[0x0c] 1362 1 T42 1 T30 4 T89 1
valid_sources[0x0d] 1378 1 T134 1 T89 1 T147 1
valid_sources[0x0e] 1316 1 T39 1 T85 1 T90 1
valid_sources[0x0f] 1303 1 T85 4 T20 2 T30 1
valid_sources[0x10] 1405 1 T85 3 T86 1 T137 1
valid_sources[0x11] 1367 1 T113 8 T114 1 T71 7
valid_sources[0x12] 1359 1 T30 2 T141 1 T148 1
valid_sources[0x13] 1429 1 T142 1 T30 2 T89 1
valid_sources[0x14] 1347 1 T84 2 T85 1 T30 1
valid_sources[0x15] 1427 1 T3 1 T113 1 T89 1
valid_sources[0x16] 1417 1 T85 1 T86 1 T90 1
valid_sources[0x17] 1437 1 T114 1 T24 2 T140 7
valid_sources[0x18] 1347 1 T2 1 T37 1 T85 1
valid_sources[0x19] 1297 1 T147 1 T149 2 T14 247
valid_sources[0x1a] 1400 1 T86 1 T150 1 T151 2
valid_sources[0x1b] 1376 1 T114 3 T134 3 T30 2
valid_sources[0x1c] 1369 1 T24 1 T37 2 T85 1
valid_sources[0x1d] 1389 1 T39 1 T137 1 T152 2
valid_sources[0x1e] 1428 1 T41 1 T28 1 T89 2
valid_sources[0x1f] 1433 1 T23 1 T86 1 T20 1
valid_sources[0x20] 1394 1 T2 3 T142 1 T14 239
valid_sources[0x21] 1413 1 T3 1 T17 32 T39 2
valid_sources[0x22] 1363 1 T114 1 T86 1 T42 1
valid_sources[0x23] 1392 1 T114 1 T153 1 T85 1
valid_sources[0x24] 1356 1 T86 1 T41 4 T140 3
valid_sources[0x25] 1364 1 T136 1 T134 1 T89 1
valid_sources[0x26] 1269 1 T85 1 T86 1 T89 1
valid_sources[0x27] 1331 1 T154 3 T14 251 T54 2
valid_sources[0x28] 1411 1 T137 1 T30 2 T91 1
valid_sources[0x29] 1428 1 T10 1 T19 3 T113 1
valid_sources[0x2a] 1381 1 T86 2 T41 1 T142 1
valid_sources[0x2b] 1327 1 T85 2 T141 1 T150 2
valid_sources[0x2c] 1426 1 T154 1 T150 1 T14 255
valid_sources[0x2d] 1456 1 T85 2 T136 1 T89 1
valid_sources[0x2e] 1306 1 T23 4 T86 1 T142 1
valid_sources[0x2f] 1368 1 T30 2 T89 2 T91 1
valid_sources[0x30] 1510 1 T30 1 T150 1 T146 1
valid_sources[0x31] 1382 1 T3 1 T12 1 T142 1
valid_sources[0x32] 1427 1 T12 4 T35 1 T155 32
valid_sources[0x33] 1334 1 T39 1 T89 3 T154 2
valid_sources[0x34] 1383 1 T156 3 T150 2 T14 230
valid_sources[0x35] 1377 1 T113 4 T30 2 T91 1
valid_sources[0x36] 1304 1 T86 1 T30 1 T154 1
valid_sources[0x37] 1346 1 T37 1 T85 2 T136 1
valid_sources[0x38] 1327 1 T3 1 T85 1 T136 1
valid_sources[0x39] 1268 1 T154 1 T146 2 T157 2
valid_sources[0x3a] 1341 1 T85 1 T86 1 T89 3
valid_sources[0x3b] 1359 1 T114 2 T39 1 T137 1
valid_sources[0x3c] 1463 1 T37 2 T142 1 T89 1
valid_sources[0x3d] 1442 1 T2 2 T84 10 T39 1
valid_sources[0x3e] 1454 1 T85 1 T142 2 T128 24
valid_sources[0x3f] 1330 1 T85 1 T137 1 T91 1
valid_sources[0x40] 1277 1 T3 1 T86 2 T140 2
valid_sources[0x41] 1359 1 T85 1 T70 2 T156 1
valid_sources[0x42] 1313 1 T2 2 T85 2 T30 1
valid_sources[0x43] 1364 1 T43 1 T134 2 T30 1
valid_sources[0x44] 1351 1 T39 1 T86 1 T137 1
valid_sources[0x45] 1332 1 T3 1 T136 2 T158 1
valid_sources[0x46] 1693 1 T39 1 T85 1 T137 1
valid_sources[0x47] 1336 1 T85 2 T30 2 T89 1
valid_sources[0x48] 1351 1 T35 1 T91 1 T140 3
valid_sources[0x49] 1479 1 T113 3 T30 2 T90 1
valid_sources[0x4a] 1361 1 T10 2 T114 3 T86 1
valid_sources[0x4b] 1405 1 T85 2 T88 15 T134 1
valid_sources[0x4c] 1509 1 T24 1 T85 1 T41 2
valid_sources[0x4d] 1387 1 T10 1 T19 1 T114 2
valid_sources[0x4e] 1449 1 T85 2 T147 1 T154 1
valid_sources[0x4f] 1434 1 T30 1 T89 2 T90 1
valid_sources[0x50] 1306 1 T114 2 T39 1 T85 1
valid_sources[0x51] 1437 1 T2 2 T39 1 T85 2
valid_sources[0x52] 1415 1 T2 3 T114 4 T159 1
valid_sources[0x53] 1400 1 T42 1 T20 1 T89 1
valid_sources[0x54] 1298 1 T12 4 T160 1 T140 3
valid_sources[0x55] 1426 1 T12 5 T39 1 T136 1
valid_sources[0x56] 1370 1 T113 3 T85 1 T137 1
valid_sources[0x57] 1382 1 T114 2 T86 1 T161 2
valid_sources[0x58] 1323 1 T85 1 T89 1 T91 1
valid_sources[0x59] 1318 1 T3 1 T37 3 T70 5
valid_sources[0x5a] 1355 1 T37 2 T137 1 T147 1
valid_sources[0x5b] 1434 1 T85 1 T152 1 T150 1
valid_sources[0x5c] 1497 1 T84 15 T85 1 T30 1
valid_sources[0x5d] 1341 1 T72 11 T89 1 T91 1
valid_sources[0x5e] 1391 1 T23 2 T37 2 T85 6
valid_sources[0x5f] 1394 1 T85 1 T137 2 T88 1
valid_sources[0x60] 1465 1 T3 1 T39 1 T85 1
valid_sources[0x61] 1347 1 T89 1 T161 1 T21 1
valid_sources[0x62] 1375 1 T3 1 T85 2 T86 2
valid_sources[0x63] 1503 1 T9 1 T114 2 T85 1
valid_sources[0x64] 1421 1 T39 1 T86 2 T136 1
valid_sources[0x65] 1582 1 T44 1 T38 32 T85 1
valid_sources[0x66] 1364 1 T85 1 T30 1 T89 3
valid_sources[0x67] 1445 1 T2 1 T12 2 T37 2
valid_sources[0x68] 1397 1 T24 1 T42 1 T142 1
valid_sources[0x69] 1306 1 T3 1 T42 1 T28 1
valid_sources[0x6a] 1524 1 T114 1 T39 1 T85 1
valid_sources[0x6b] 1402 1 T86 1 T134 1 T30 1
valid_sources[0x6c] 1373 1 T4 16 T85 1 T142 1
valid_sources[0x6d] 1392 1 T2 2 T85 2 T30 2
valid_sources[0x6e] 1399 1 T162 2 T163 1 T14 262
valid_sources[0x6f] 1426 1 T30 1 T149 1 T141 2
valid_sources[0x70] 1413 1 T114 1 T137 1 T40 26
valid_sources[0x71] 1409 1 T10 1 T37 1 T85 1
valid_sources[0x72] 1318 1 T3 1 T41 1 T136 1
valid_sources[0x73] 1378 1 T12 1 T14 243 T54 1
valid_sources[0x74] 1352 1 T147 1 T14 254 T164 1
valid_sources[0x75] 1340 1 T136 2 T142 1 T134 1
valid_sources[0x76] 1471 1 T114 1 T89 1 T165 1
valid_sources[0x77] 1332 1 T136 1 T14 243 T166 2
valid_sources[0x78] 1331 1 T88 5 T147 1 T167 2
valid_sources[0x79] 1436 1 T7 1 T154 1 T168 15
valid_sources[0x7a] 1405 1 T19 4 T114 1 T37 1
valid_sources[0x7b] 1286 1 T89 1 T14 229 T15 325
valid_sources[0x7c] 1361 1 T84 1 T39 1 T141 1
valid_sources[0x7d] 1397 1 T10 1 T85 1 T86 1
valid_sources[0x7e] 1395 1 T113 1 T137 1 T149 1
valid_sources[0x7f] 1403 1 T37 2 T86 1 T168 9
valid_sources[0x80] 1286 1 T89 1 T156 1 T169 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 81605 1 T1 1 T2 18 T3 15
values[0x0] all_enables biggest_size 119850 1 T5 2 T23 1 T24 2
values[0x1] all_enables biggest_size 119888 1 T23 2 T72 1 T152 2

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