Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg

Group : cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64
tl_intg_err_cgs_wrap[rom_ctrl_regs_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	100.00

Variables for Group Instance tl_intg_err_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_mem	2	1	1	50.00	100	0	0	2
cp_num_cmd_err_bits	4	0	4	100.00	100	1	1	0
cp_num_data_err_bits	4	0	4	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0

---

Group Instance : tl_intg_err_cgs_wrap[rom_ctrl_regs_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_cgs_wrap[rom_ctrl_regs_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	100.00

Variables for Group Instance tl_intg_err_cgs_wrap[rom_ctrl_regs_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_mem	2	1	1	50.00	100	0	0	2
cp_num_cmd_err_bits	4	0	4	100.00	100	1	1	0
cp_num_data_err_bits	4	0	4	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0

Summary for Variable cp_is_mem

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_is_mem

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
[auto[0]]	0	0			-	-		-	-		-	-
auto[1]	1218641	0			T2	81		T3	70		T4	2

---

Summary for Variable cp_num_cmd_err_bits

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_num_cmd_err_bits

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1218446	1			T2	81		T3	70		T4	2
values[1]	20	1			T62	5		T63	1		T116	2
values[2]	3	1			T117	1		T118	2		-	-
values[3]	98	1			T51	4		T62	3		T63	5

---

Summary for Variable cp_num_data_err_bits

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_num_data_err_bits

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1218424	1			T2	81		T3	70		T4	2
values[1]	22	1			T51	1		T62	2		T63	2
values[2]	6	1			T119	1		T120	1		T121	1
values[3]	102	1			T51	2		T62	8		T63	3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1218331	1			T2	81		T3	70		T4	2
auto[TlIntgErrCmd]	93	1			T51	3		T62	5		T63	2
auto[TlIntgErrData]	115	1			T51	3		T62	5		T63	3
auto[TlIntgErrBoth]	102	1			T51	4		T62	10		T63	5

Summary for Variable cp_is_mem

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_is_mem

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
[auto[1]]	0	0			-	-		-	-		-	-
auto[0]	979682	0			T1	1		T2	32		T3	32

---

Summary for Variable cp_num_cmd_err_bits

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_num_cmd_err_bits

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	979480	1			T1	1		T2	32		T3	32
values[1]	19	1			T62	1		T63	1		T119	2
values[2]	3	1			T63	1		T122	1		T123	1
values[3]	104	1			T51	5		T62	7		T63	1

---

Summary for Variable cp_num_data_err_bits

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_num_data_err_bits

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	979469	1			T1	1		T2	32		T3	32
values[1]	26	1			T51	2		T62	3		T63	1
values[2]	6	1			T124	1		T121	1		T117	1
values[3]	101	1			T51	4		T62	6		T63	3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	979372	1			T1	1		T2	32		T3	32
auto[TlIntgErrCmd]	97	1			T51	2		T62	6		T63	3
auto[TlIntgErrData]	108	1			T51	3		T62	8		T63	5
auto[TlIntgErrBoth]	105	1			T51	5		T62	6		T63	2