Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

744030

1

T2

74

T3

64

T6

203

full_word

474611

1

T2

7

T3

6

T4

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1218331	1			T2	81		T3	70		T4	2
auto[TlIntgErrCmd]	93	1			T51	3		T62	5		T63	2
auto[TlIntgErrData]	115	1			T51	3		T62	5		T63	3
auto[TlIntgErrBoth]	102	1			T51	4		T62	10		T63	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

209050

1

T2

81

T3

70

T4

2

auto[1]

1009591

1

T14

207905

T15

257992

T16

137762

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	94883	1			T2	74		T3	64		T6	203
auto[TlIntgErrNone]	partial	auto[1]	648867	1			T14	131939		T15	166725		T16	88359
auto[TlIntgErrNone]	full_word	auto[0]	114034	1			T2	7		T3	6		T4	2
auto[TlIntgErrNone]	full_word	auto[1]	360547	1			T14	75966		T15	91267		T16	49403
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T62	3		T63	2		T119	1
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T51	2		T62	2		T119	5
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T51	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T119	2		T116	1		T117	1
auto[TlIntgErrData]	partial	auto[0]	46	1			T51	2		T62	3		T63	1
auto[TlIntgErrData]	partial	auto[1]	59	1			T51	1		T62	2		T63	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T119	2		T124	1		T125	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T126	1		T122	1		T125	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T51	2		T62	4		T63	3
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T62	5		T63	2		T119	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T126	1		T122	2		T127	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T51	2		T62	1		T121	2