Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	74557	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1776165

1

T3

6

T5

12

T6

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	483884	1			T3	6		T5	12		T6	81
values[0x0]	670204	1			T15	17991		T16	27352		T17	36270
values[0x1]	696634	1			T15	18879		T16	28429		T17	37094

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	38586	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1812136

1

T3

6

T5

12

T6

50

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7543	1			T8	3		T18	1		T24	2
valid_sources[0x01]	7855	1			T18	2		T26	1		T14	2
valid_sources[0x02]	7897	1			T5	1		T8	1		T18	1
valid_sources[0x03]	7124	1			T12	1		T26	2		T102	2
valid_sources[0x04]	6646	1			T5	1		T8	2		T18	2
valid_sources[0x05]	7412	1			T24	1		T12	1		T102	1
valid_sources[0x06]	6623	1			T18	1		T26	1		T102	1
valid_sources[0x07]	7453	1			T8	1		T18	1		T14	1
valid_sources[0x08]	7591	1			T8	2		T26	2		T22	11
valid_sources[0x09]	7407	1			T26	2		T102	4		T37	3
valid_sources[0x0a]	5530	1			T18	2		T24	1		T102	11
valid_sources[0x0b]	7200	1			T3	1		T8	1		T18	1
valid_sources[0x0c]	5934	1			T8	1		T14	1		T16	140
valid_sources[0x0d]	7355	1			T8	1		T61	4		T23	2
valid_sources[0x0e]	6673	1			T8	1		T18	2		T61	1
valid_sources[0x0f]	6315	1			T18	1		T14	2		T16	810
valid_sources[0x10]	6891	1			T102	1		T15	8		T16	121
valid_sources[0x11]	7806	1			T8	2		T26	5		T102	1
valid_sources[0x12]	7033	1			T5	1		T8	1		T22	6
valid_sources[0x13]	6411	1			T12	2		T26	1		T16	20
valid_sources[0x14]	8081	1			T8	1		T12	1		T14	3
valid_sources[0x15]	7258	1			T18	2		T12	1		T102	3
valid_sources[0x16]	7840	1			T8	1		T18	1		T15	963
valid_sources[0x17]	5879	1			T18	1		T16	5		T43	1
valid_sources[0x18]	6519	1			T8	2		T23	5		T16	8
valid_sources[0x19]	6171	1			T8	2		T24	1		T26	1
valid_sources[0x1a]	7086	1			T18	1		T14	1		T15	299
valid_sources[0x1b]	8270	1			T8	1		T18	2		T26	1
valid_sources[0x1c]	8012	1			T6	41		T18	1		T12	2
valid_sources[0x1d]	8105	1			T8	2		T24	2		T14	1
valid_sources[0x1e]	7444	1			T12	1		T102	2		T14	3
valid_sources[0x1f]	6561	1			T8	1		T102	3		T15	269
valid_sources[0x20]	7178	1			T12	2		T16	470		T40	1
valid_sources[0x21]	6221	1			T8	1		T12	1		T26	2
valid_sources[0x22]	6926	1			T8	1		T24	1		T26	1
valid_sources[0x23]	9076	1			T8	1		T102	1		T14	1
valid_sources[0x24]	7443	1			T8	1		T24	2		T15	3
valid_sources[0x25]	7615	1			T13	19		T102	2		T14	1
valid_sources[0x26]	7723	1			T8	1		T18	1		T26	1
valid_sources[0x27]	7817	1			T18	2		T24	1		T13	25
valid_sources[0x28]	6677	1			T8	2		T102	6		T23	7
valid_sources[0x29]	7286	1			T8	2		T18	2		T61	6
valid_sources[0x2a]	7332	1			T8	1		T18	2		T24	2
valid_sources[0x2b]	6485	1			T18	2		T14	1		T15	93
valid_sources[0x2c]	5631	1			T8	2		T12	2		T102	5
valid_sources[0x2d]	7445	1			T8	2		T18	2		T26	1
valid_sources[0x2e]	7120	1			T12	5		T26	1		T15	293
valid_sources[0x2f]	6915	1			T18	3		T26	2		T23	4
valid_sources[0x30]	7304	1			T8	2		T18	2		T12	1
valid_sources[0x31]	7139	1			T8	2		T61	5		T16	287
valid_sources[0x32]	6932	1			T12	1		T14	1		T23	2
valid_sources[0x33]	7339	1			T8	2		T12	3		T102	2
valid_sources[0x34]	7020	1			T102	9		T15	393		T16	318
valid_sources[0x35]	7548	1			T8	2		T23	3		T15	94
valid_sources[0x36]	7673	1			T12	4		T26	2		T14	4
valid_sources[0x37]	7881	1			T8	2		T12	1		T15	226
valid_sources[0x38]	8213	1			T18	1		T26	2		T118	1
valid_sources[0x39]	9412	1			T18	1		T12	3		T26	3
valid_sources[0x3a]	6317	1			T8	1		T18	2		T24	2
valid_sources[0x3b]	6727	1			T12	1		T16	255		T119	3
valid_sources[0x3c]	8013	1			T8	1		T102	1		T23	2
valid_sources[0x3d]	6082	1			T12	1		T14	1		T15	490
valid_sources[0x3e]	6701	1			T18	2		T102	1		T23	2
valid_sources[0x3f]	7336	1			T8	2		T24	1		T12	1
valid_sources[0x40]	5438	1			T8	1		T18	1		T26	4
valid_sources[0x41]	7327	1			T26	2		T102	1		T15	137
valid_sources[0x42]	5952	1			T18	1		T15	152		T16	11
valid_sources[0x43]	5874	1			T8	2		T12	4		T26	3
valid_sources[0x44]	10859	1			T8	1		T24	2		T12	1
valid_sources[0x45]	8418	1			T8	1		T26	2		T102	6
valid_sources[0x46]	7779	1			T12	1		T102	5		T15	16
valid_sources[0x47]	6703	1			T8	1		T102	1		T15	579
valid_sources[0x48]	6622	1			T18	1		T26	1		T14	1
valid_sources[0x49]	6473	1			T8	1		T18	1		T26	3
valid_sources[0x4a]	6673	1			T8	3		T16	88		T37	6
valid_sources[0x4b]	8482	1			T8	1		T12	2		T22	1
valid_sources[0x4c]	6109	1			T24	1		T12	1		T102	1
valid_sources[0x4d]	6926	1			T18	1		T12	3		T102	7
valid_sources[0x4e]	6772	1			T102	2		T16	191		T40	1
valid_sources[0x4f]	6713	1			T8	1		T18	3		T12	1
valid_sources[0x50]	7459	1			T12	1		T26	3		T15	72
valid_sources[0x51]	6070	1			T26	1		T16	171		T120	1
valid_sources[0x52]	6568	1			T8	1		T18	2		T12	2
valid_sources[0x53]	7723	1			T26	1		T102	3		T16	144
valid_sources[0x54]	5544	1			T12	3		T102	4		T16	131
valid_sources[0x55]	9095	1			T8	2		T12	3		T23	1
valid_sources[0x56]	6130	1			T8	1		T102	1		T61	3
valid_sources[0x57]	8250	1			T6	17		T12	2		T102	4
valid_sources[0x58]	7756	1			T12	2		T15	1056		T33	90
valid_sources[0x59]	7310	1			T18	1		T12	3		T26	1
valid_sources[0x5a]	7266	1			T8	1		T15	375		T16	123
valid_sources[0x5b]	6132	1			T26	3		T14	2		T16	163
valid_sources[0x5c]	7294	1			T5	1		T14	1		T15	336
valid_sources[0x5d]	7714	1			T8	1		T26	2		T14	1
valid_sources[0x5e]	7198	1			T12	1		T26	1		T102	1
valid_sources[0x5f]	7842	1			T3	1		T5	1		T8	1
valid_sources[0x60]	7713	1			T8	3		T14	3		T61	1
valid_sources[0x61]	6966	1			T5	1		T26	2		T14	3
valid_sources[0x62]	8364	1			T8	2		T14	3		T61	2
valid_sources[0x63]	7124	1			T18	1		T26	2		T22	9
valid_sources[0x64]	6605	1			T12	2		T15	113		T16	790
valid_sources[0x65]	6411	1			T18	1		T26	4		T14	3
valid_sources[0x66]	6702	1			T8	1		T18	1		T12	1
valid_sources[0x67]	7870	1			T8	2		T18	2		T14	3
valid_sources[0x68]	5781	1			T12	7		T14	2		T61	1
valid_sources[0x69]	7547	1			T5	1		T8	2		T14	2
valid_sources[0x6a]	6406	1			T8	2		T12	3		T61	3
valid_sources[0x6b]	7271	1			T8	1		T18	1		T12	2
valid_sources[0x6c]	7146	1			T8	2		T18	3		T12	1
valid_sources[0x6d]	8083	1			T12	1		T14	1		T16	26
valid_sources[0x6e]	7294	1			T8	3		T24	2		T26	2
valid_sources[0x6f]	8084	1			T8	2		T18	1		T102	2
valid_sources[0x70]	8160	1			T12	1		T26	1		T102	1
valid_sources[0x71]	5860	1			T12	1		T15	116		T74	4
valid_sources[0x72]	7095	1			T8	1		T18	1		T24	1
valid_sources[0x73]	8234	1			T8	2		T12	3		T102	2
valid_sources[0x74]	6360	1			T61	1		T15	2		T120	1
valid_sources[0x75]	8508	1			T24	1		T26	1		T14	1
valid_sources[0x76]	6703	1			T18	2		T24	1		T26	1
valid_sources[0x77]	6420	1			T9	13		T12	2		T23	1
valid_sources[0x78]	6180	1			T8	1		T18	4		T12	1
valid_sources[0x79]	6312	1			T18	1		T14	2		T15	12
valid_sources[0x7a]	6935	1			T8	1		T26	2		T102	4
valid_sources[0x7b]	7979	1			T8	1		T18	2		T16	832
valid_sources[0x7c]	6848	1			T18	2		T102	3		T15	179
valid_sources[0x7d]	8182	1			T8	1		T24	1		T26	1
valid_sources[0x7e]	6981	1			T12	1		T15	197		T16	654
valid_sources[0x7f]	7373	1			T8	3		T18	1		T26	3
valid_sources[0x80]	7207	1			T8	1		T24	1		T12	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

446481

1

T3

6

T5

12

T6

10

values[0x0]

all_enables

biggest_size

664283

1

T15

17827

T16

27103

T17

35958

values[0x1]

all_enables

biggest_size

665401

1

T15

18021

T16

27095

T17

35433

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	134208	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1352781

1

T1

5

T2

1

T3

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	372797	1			T2	1		T3	13		T5	43
values[0x0]	516043	1			T1	6		T4	5		T7	4
values[0x1]	598149	1			T1	10		T4	10		T7	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	60241	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1426748

1

T1

8

T2

1

T3

8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6457	1			T15	145		T16	234		T121	1
valid_sources[0x01]	5352	1			T12	2		T15	145		T16	248
valid_sources[0x02]	5372	1			T15	138		T16	265		T121	2
valid_sources[0x03]	5889	1			T23	1		T15	137		T16	254
valid_sources[0x04]	5381	1			T12	1		T15	132		T16	249
valid_sources[0x05]	5106	1			T10	9		T12	1		T15	143
valid_sources[0x06]	6111	1			T22	1		T15	147		T16	267
valid_sources[0x07]	5078	1			T15	173		T16	238		T35	1
valid_sources[0x08]	5605	1			T15	145		T16	245		T121	2
valid_sources[0x09]	5411	1			T23	1		T15	155		T16	227
valid_sources[0x0a]	5699	1			T22	1		T23	1		T15	166
valid_sources[0x0b]	5961	1			T14	1		T15	138		T16	242
valid_sources[0x0c]	5088	1			T64	2		T15	144		T16	226
valid_sources[0x0d]	5302	1			T15	163		T16	249		T37	1
valid_sources[0x0e]	5807	1			T14	2		T15	147		T16	268
valid_sources[0x0f]	5731	1			T9	3		T12	2		T15	144
valid_sources[0x10]	5825	1			T12	1		T42	1		T14	4
valid_sources[0x11]	5890	1			T9	1		T15	147		T16	256
valid_sources[0x12]	5810	1			T5	3		T14	4		T23	1
valid_sources[0x13]	5835	1			T5	2		T26	4		T23	2
valid_sources[0x14]	6077	1			T23	1		T15	159		T16	209
valid_sources[0x15]	6138	1			T15	155		T16	210		T37	4
valid_sources[0x16]	5891	1			T5	1		T12	3		T26	2
valid_sources[0x17]	5815	1			T6	1		T23	1		T15	147
valid_sources[0x18]	5043	1			T26	1		T15	123		T16	216
valid_sources[0x19]	5809	1			T24	3		T14	4		T15	143
valid_sources[0x1a]	5737	1			T15	159		T16	249		T17	339
valid_sources[0x1b]	5906	1			T12	1		T22	1		T15	143
valid_sources[0x1c]	5573	1			T15	134		T16	242		T56	8
valid_sources[0x1d]	5848	1			T15	134		T16	258		T17	282
valid_sources[0x1e]	7088	1			T23	1		T15	157		T16	250
valid_sources[0x1f]	5884	1			T12	1		T22	2		T15	142
valid_sources[0x20]	6068	1			T24	13		T26	6		T15	163
valid_sources[0x21]	5776	1			T22	2		T14	1		T23	2
valid_sources[0x22]	6389	1			T12	2		T15	168		T16	275
valid_sources[0x23]	5587	1			T26	1		T22	1		T42	4
valid_sources[0x24]	5849	1			T1	8		T23	1		T15	133
valid_sources[0x25]	6198	1			T6	2		T12	1		T15	150
valid_sources[0x26]	6151	1			T12	2		T14	1		T15	164
valid_sources[0x27]	5100	1			T12	4		T15	156		T16	256
valid_sources[0x28]	5821	1			T12	2		T14	4		T23	1
valid_sources[0x29]	6307	1			T12	1		T15	121		T16	258
valid_sources[0x2a]	6713	1			T47	1		T12	1		T14	2
valid_sources[0x2b]	5285	1			T15	139		T16	267		T17	299
valid_sources[0x2c]	5884	1			T12	2		T15	144		T16	233
valid_sources[0x2d]	5782	1			T12	1		T26	1		T15	138
valid_sources[0x2e]	5115	1			T22	1		T14	1		T15	137
valid_sources[0x2f]	5484	1			T15	145		T16	232		T45	1
valid_sources[0x30]	6298	1			T5	1		T15	137		T16	250
valid_sources[0x31]	6323	1			T6	2		T15	144		T16	248
valid_sources[0x32]	5105	1			T15	146		T16	232		T121	1
valid_sources[0x33]	6074	1			T24	2		T15	144		T16	274
valid_sources[0x34]	6296	1			T14	1		T15	169		T16	244
valid_sources[0x35]	5562	1			T14	1		T15	127		T16	220
valid_sources[0x36]	6013	1			T47	1		T15	148		T16	272
valid_sources[0x37]	6124	1			T15	132		T16	229		T17	348
valid_sources[0x38]	6183	1			T12	1		T26	2		T23	2
valid_sources[0x39]	5642	1			T6	1		T12	1		T26	1
valid_sources[0x3a]	5980	1			T15	159		T16	253		T17	262
valid_sources[0x3b]	5645	1			T26	2		T15	161		T16	218
valid_sources[0x3c]	5547	1			T12	1		T15	106		T16	243
valid_sources[0x3d]	5279	1			T26	1		T14	1		T15	176
valid_sources[0x3e]	6383	1			T23	1		T15	155		T16	243
valid_sources[0x3f]	5973	1			T12	1		T14	2		T61	32
valid_sources[0x40]	5859	1			T1	1		T3	13		T12	1
valid_sources[0x41]	5905	1			T26	1		T23	2		T15	168
valid_sources[0x42]	6543	1			T14	1		T15	124		T16	254
valid_sources[0x43]	5136	1			T15	159		T16	259		T17	304
valid_sources[0x44]	6955	1			T15	146		T16	235		T121	3
valid_sources[0x45]	5593	1			T15	151		T16	263		T121	2
valid_sources[0x46]	5492	1			T15	135		T16	275		T17	286
valid_sources[0x47]	5472	1			T14	1		T15	158		T16	255
valid_sources[0x48]	6307	1			T12	1		T15	164		T16	240
valid_sources[0x49]	5645	1			T23	2		T15	159		T16	259
valid_sources[0x4a]	6115	1			T15	138		T16	255		T40	4
valid_sources[0x4b]	5849	1			T5	2		T7	1		T26	1
valid_sources[0x4c]	6464	1			T7	3		T15	156		T16	220
valid_sources[0x4d]	5485	1			T6	3		T15	159		T16	272
valid_sources[0x4e]	5993	1			T5	1		T12	1		T23	1
valid_sources[0x4f]	5198	1			T22	1		T64	1		T15	138
valid_sources[0x50]	6155	1			T23	1		T15	146		T16	247
valid_sources[0x51]	4989	1			T6	2		T26	2		T14	3
valid_sources[0x52]	6858	1			T26	3		T15	148		T16	196
valid_sources[0x53]	5286	1			T12	1		T23	1		T15	182
valid_sources[0x54]	6644	1			T15	155		T16	247		T122	1
valid_sources[0x55]	5671	1			T5	1		T26	2		T14	3
valid_sources[0x56]	5480	1			T12	1		T23	1		T15	147
valid_sources[0x57]	5816	1			T12	2		T14	1		T23	1
valid_sources[0x58]	6193	1			T15	158		T16	250		T121	1
valid_sources[0x59]	5279	1			T23	1		T15	146		T16	253
valid_sources[0x5a]	5357	1			T5	1		T6	2		T15	174
valid_sources[0x5b]	6503	1			T5	2		T12	1		T15	158
valid_sources[0x5c]	6641	1			T9	7		T23	1		T15	179
valid_sources[0x5d]	5571	1			T15	147		T16	236		T36	1
valid_sources[0x5e]	5776	1			T12	1		T15	129		T16	235
valid_sources[0x5f]	5982	1			T9	2		T26	1		T15	136
valid_sources[0x60]	5360	1			T22	1		T15	147		T16	271
valid_sources[0x61]	5663	1			T14	4		T15	147		T16	231
valid_sources[0x62]	5282	1			T6	1		T15	145		T16	206
valid_sources[0x63]	6155	1			T9	6		T14	3		T15	158
valid_sources[0x64]	5097	1			T14	3		T15	145		T16	230
valid_sources[0x65]	5770	1			T25	36		T12	2		T26	2
valid_sources[0x66]	5563	1			T15	166		T16	266		T17	269
valid_sources[0x67]	6200	1			T15	130		T16	247		T121	1
valid_sources[0x68]	5454	1			T12	2		T22	1		T15	159
valid_sources[0x69]	6227	1			T5	1		T14	4		T23	1
valid_sources[0x6a]	5462	1			T12	2		T15	143		T16	234
valid_sources[0x6b]	5552	1			T30	1		T26	1		T14	4
valid_sources[0x6c]	5767	1			T64	1		T15	133		T16	244
valid_sources[0x6d]	5930	1			T12	2		T26	3		T15	157
valid_sources[0x6e]	5657	1			T24	2		T15	144		T16	228
valid_sources[0x6f]	5709	1			T1	2		T14	2		T23	1
valid_sources[0x70]	5636	1			T26	1		T15	145		T16	244
valid_sources[0x71]	5949	1			T5	3		T9	5		T12	1
valid_sources[0x72]	6457	1			T12	1		T14	1		T15	155
valid_sources[0x73]	5790	1			T26	2		T15	149		T16	218
valid_sources[0x74]	5959	1			T42	1		T15	157		T16	280
valid_sources[0x75]	5948	1			T23	1		T15	128		T16	277
valid_sources[0x76]	5628	1			T15	146		T16	261		T17	329
valid_sources[0x77]	5181	1			T15	139		T16	251		T57	1
valid_sources[0x78]	5833	1			T26	1		T15	171		T16	277
valid_sources[0x79]	6458	1			T14	1		T15	153		T16	226
valid_sources[0x7a]	5602	1			T24	1		T12	1		T26	2
valid_sources[0x7b]	5972	1			T15	153		T16	244		T17	266
valid_sources[0x7c]	6294	1			T24	1		T12	1		T15	153
valid_sources[0x7d]	5497	1			T23	1		T15	165		T16	241
valid_sources[0x7e]	5746	1			T23	3		T15	161		T16	224
valid_sources[0x7f]	6085	1			T26	2		T15	143		T16	225
valid_sources[0x80]	5331	1			T14	1		T15	162		T16	256

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

342936

1

T2

1

T3

8

T5

25

values[0x0]

all_enables

biggest_size

505178

1

T1

4

T4

2

T7

1

values[0x1]

all_enables

biggest_size

504667

1

T1

1

T4

3

T7

2