Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3314690

1

T6

71

T8

190

T9

75

full_word

2079319

1

T3

4

T5

8

T6

10

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	5393719	1			T3	4		T5	8		T6	81
auto[TlIntgErrCmd]	92	1			T58	3		T59	4		T60	8
auto[TlIntgErrData]	101	1			T58	4		T59	3		T60	1
auto[TlIntgErrBoth]	97	1			T58	3		T59	3		T60	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

851533

1

T3

4

T5

8

T6

81

auto[1]

4542476

1

T15

124546

T16

187272

T17

243205

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	361173	1			T6	71		T8	190		T9	75
auto[TlIntgErrNone]	partial	auto[1]	2953247	1			T15	81421		T16	122369		T17	158029
auto[TlIntgErrNone]	full_word	auto[0]	490226	1			T3	4		T5	8		T6	10
auto[TlIntgErrNone]	full_word	auto[1]	1589073	1			T15	43125		T16	64903		T17	85176
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T58	2		T59	2		T60	5
auto[TlIntgErrCmd]	partial	auto[1]	40	1			T58	1		T59	1		T60	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T59	1		T106	1		T113	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T112	1		T114	1		T105	2
auto[TlIntgErrData]	partial	auto[0]	49	1			T58	2		T59	2		T60	1
auto[TlIntgErrData]	partial	auto[1]	43	1			T58	2		T107	3		T108	4
auto[TlIntgErrData]	full_word	auto[0]	2	1			T109	1		T105	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	7	1			T59	1		T115	1		T116	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T58	1		T59	3		T60	1
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T58	2		T107	3		T108	4
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T114	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T115	1		T117	1		T110	1