Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3110035

1

T2

188

T5

71

T8

200

full_word

1979064

1

T2

14

T5

5

T8

20

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	5088769	1			T2	202		T5	76		T8	220
auto[TlIntgErrCmd]	106	1			T53	2		T54	8		T55	5
auto[TlIntgErrData]	121	1			T53	4		T54	10		T55	3
auto[TlIntgErrBoth]	103	1			T53	4		T54	2		T55	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

808149

1

T2

202

T5

76

T8

220

auto[1]

4280950

1

T11

101285

T12

488878

T13

143822

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	340567	1			T2	188		T5	71		T8	200
auto[TlIntgErrNone]	partial	auto[1]	2769167	1			T11	66569		T12	313473		T13	93458
auto[TlIntgErrNone]	full_word	auto[0]	467435	1			T2	14		T5	5		T8	20
auto[TlIntgErrNone]	full_word	auto[1]	1511600	1			T11	34716		T12	175405		T13	50364
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T53	1		T54	1		T55	3
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T53	1		T54	7		T55	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T109	1		T106	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T110	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	51	1			T53	2		T54	4		T55	3
auto[TlIntgErrData]	partial	auto[1]	57	1			T53	2		T54	5		T104	1
auto[TlIntgErrData]	full_word	auto[0]	8	1			T54	1		T109	2		T111	3
auto[TlIntgErrData]	full_word	auto[1]	5	1			T109	2		T112	2		T113	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T55	1		T103	3		T107	1
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T53	4		T54	2		T104	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T105	1		T111	1		T112	2
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T55	1		T107	2		T108	1