Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	75185	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1908323

1

T1

6

T2

15

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	515577	1			T1	74		T2	145		T3	6
values[0x0]	720547	1			T11	49465		T12	45382		T13	98541
values[0x1]	747384	1			T11	51406		T12	47272		T13	102188

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	39011	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1944497

1

T1

44

T2

92

T3

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8401	1			T11	263		T12	557		T13	1473
valid_sources[0x01]	7634	1			T2	2		T11	366		T12	473
valid_sources[0x02]	8917	1			T2	3		T11	944		T12	499
valid_sources[0x03]	7988	1			T11	891		T12	461		T13	661
valid_sources[0x04]	7712	1			T15	1		T49	1		T16	1
valid_sources[0x05]	9978	1			T7	10		T11	1290		T12	507
valid_sources[0x06]	7368	1			T12	534		T13	1622		T70	1
valid_sources[0x07]	8152	1			T14	1		T15	1		T11	1084
valid_sources[0x08]	7394	1			T15	1		T12	502		T13	277
valid_sources[0x09]	7695	1			T2	1		T14	1		T15	1
valid_sources[0x0a]	7420	1			T1	2		T2	1		T14	1
valid_sources[0x0b]	7690	1			T2	3		T14	2		T15	1
valid_sources[0x0c]	7680	1			T14	3		T11	441		T12	518
valid_sources[0x0d]	6842	1			T14	1		T12	495		T17	1
valid_sources[0x0e]	8274	1			T11	888		T49	1		T12	473
valid_sources[0x0f]	8857	1			T11	378		T12	538		T13	1875
valid_sources[0x10]	6096	1			T14	1		T11	47		T12	486
valid_sources[0x11]	6100	1			T15	1		T11	489		T12	506
valid_sources[0x12]	7206	1			T2	2		T11	696		T49	1
valid_sources[0x13]	7392	1			T49	1		T12	498		T13	1069
valid_sources[0x14]	8674	1			T2	1		T11	1027		T12	439
valid_sources[0x15]	7960	1			T14	1		T11	197		T12	516
valid_sources[0x16]	7973	1			T1	4		T15	1		T11	1074
valid_sources[0x17]	7722	1			T11	459		T12	500		T13	1202
valid_sources[0x18]	6213	1			T12	452		T17	1		T13	178
valid_sources[0x19]	8212	1			T11	1154		T12	401		T13	947
valid_sources[0x1a]	8711	1			T14	1		T15	1		T11	807
valid_sources[0x1b]	7776	1			T12	457		T13	298		T93	2
valid_sources[0x1c]	8928	1			T11	642		T12	515		T13	1207
valid_sources[0x1d]	7288	1			T2	1		T11	489		T49	1
valid_sources[0x1e]	9141	1			T11	263		T49	1		T12	477
valid_sources[0x1f]	5984	1			T12	436		T13	12		T93	1
valid_sources[0x20]	6644	1			T4	17		T11	184		T12	484
valid_sources[0x21]	7701	1			T14	3		T11	1251		T12	485
valid_sources[0x22]	6993	1			T2	1		T7	4		T14	1
valid_sources[0x23]	7813	1			T14	1		T11	249		T12	521
valid_sources[0x24]	6541	1			T11	575		T12	464		T13	237
valid_sources[0x25]	7265	1			T3	1		T4	22		T14	1
valid_sources[0x26]	5882	1			T14	4		T12	485		T17	1
valid_sources[0x27]	7721	1			T2	2		T11	3		T12	498
valid_sources[0x28]	6454	1			T2	1		T14	1		T11	3
valid_sources[0x29]	6663	1			T11	159		T12	470		T13	944
valid_sources[0x2a]	7194	1			T2	2		T14	1		T11	842
valid_sources[0x2b]	5596	1			T15	1		T11	27		T49	1
valid_sources[0x2c]	8239	1			T14	1		T11	259		T12	499
valid_sources[0x2d]	9690	1			T10	35		T11	339		T12	486
valid_sources[0x2e]	7776	1			T2	1		T15	1		T11	854
valid_sources[0x2f]	6527	1			T15	1		T11	376		T12	523
valid_sources[0x30]	7951	1			T15	1		T11	350		T12	494
valid_sources[0x31]	7991	1			T14	1		T11	389		T12	529
valid_sources[0x32]	6844	1			T15	1		T11	235		T12	458
valid_sources[0x33]	7985	1			T14	2		T15	1		T12	521
valid_sources[0x34]	8513	1			T11	588		T12	500		T13	1737
valid_sources[0x35]	7863	1			T14	2		T11	152		T12	427
valid_sources[0x36]	9426	1			T11	593		T49	1		T12	488
valid_sources[0x37]	9026	1			T14	2		T11	789		T49	2
valid_sources[0x38]	8356	1			T2	1		T14	1		T12	459
valid_sources[0x39]	6708	1			T11	367		T12	506		T13	664
valid_sources[0x3a]	8191	1			T1	12		T2	1		T14	1
valid_sources[0x3b]	8224	1			T14	1		T15	1		T11	363
valid_sources[0x3c]	8125	1			T2	2		T12	487		T13	2035
valid_sources[0x3d]	5476	1			T14	1		T15	1		T11	208
valid_sources[0x3e]	8421	1			T14	3		T11	1301		T12	493
valid_sources[0x3f]	7684	1			T2	1		T14	1		T15	1
valid_sources[0x40]	7248	1			T2	1		T14	2		T11	468
valid_sources[0x41]	8005	1			T2	3		T5	72		T11	773
valid_sources[0x42]	8430	1			T11	756		T49	2		T12	493
valid_sources[0x43]	6236	1			T11	165		T12	514		T13	339
valid_sources[0x44]	7180	1			T14	1		T11	378		T12	499
valid_sources[0x45]	9201	1			T2	1		T14	1		T15	1
valid_sources[0x46]	7714	1			T11	519		T12	510		T13	816
valid_sources[0x47]	5718	1			T2	1		T5	19		T14	1
valid_sources[0x48]	8698	1			T2	3		T11	440		T49	2
valid_sources[0x49]	7477	1			T11	576		T49	1		T12	446
valid_sources[0x4a]	8435	1			T14	2		T11	1614		T16	1
valid_sources[0x4b]	7053	1			T2	1		T11	730		T12	497
valid_sources[0x4c]	8924	1			T14	2		T15	1		T11	1441
valid_sources[0x4d]	6276	1			T12	535		T13	596		T71	2
valid_sources[0x4e]	8099	1			T2	1		T14	1		T11	541
valid_sources[0x4f]	7358	1			T2	1		T14	2		T15	1
valid_sources[0x50]	8362	1			T4	14		T11	401		T49	1
valid_sources[0x51]	7572	1			T2	1		T15	1		T11	232
valid_sources[0x52]	6882	1			T2	2		T11	67		T49	2
valid_sources[0x53]	8087	1			T2	4		T11	321		T12	514
valid_sources[0x54]	7285	1			T2	1		T14	1		T11	298
valid_sources[0x55]	7383	1			T15	1		T12	493		T13	721
valid_sources[0x56]	8415	1			T15	2		T11	769		T49	1
valid_sources[0x57]	6321	1			T14	1		T49	2		T12	476
valid_sources[0x58]	6542	1			T11	215		T12	484		T13	656
valid_sources[0x59]	6903	1			T11	1045		T12	503		T13	412
valid_sources[0x5a]	8333	1			T11	942		T12	517		T13	989
valid_sources[0x5b]	7930	1			T15	2		T11	161		T12	428
valid_sources[0x5c]	6854	1			T2	1		T14	1		T11	833
valid_sources[0x5d]	7170	1			T2	3		T12	517		T13	1071
valid_sources[0x5e]	8119	1			T2	2		T11	380		T12	450
valid_sources[0x5f]	6745	1			T12	486		T13	105		T93	1
valid_sources[0x60]	6713	1			T14	4		T11	364		T12	501
valid_sources[0x61]	6944	1			T11	1023		T12	470		T13	427
valid_sources[0x62]	7913	1			T2	1		T11	221		T12	511
valid_sources[0x63]	8034	1			T15	1		T11	840		T12	443
valid_sources[0x64]	6461	1			T11	445		T12	465		T13	472
valid_sources[0x65]	6414	1			T11	174		T12	464		T13	412
valid_sources[0x66]	9224	1			T14	1		T11	791		T12	499
valid_sources[0x67]	6745	1			T2	1		T11	56		T12	485
valid_sources[0x68]	7366	1			T11	215		T12	462		T13	817
valid_sources[0x69]	7345	1			T49	1		T12	436		T13	1757
valid_sources[0x6a]	6337	1			T10	22		T12	495		T13	571
valid_sources[0x6b]	8074	1			T2	1		T11	265		T49	1
valid_sources[0x6c]	7381	1			T11	596		T49	1		T12	438
valid_sources[0x6d]	7092	1			T11	416		T12	491		T13	1235
valid_sources[0x6e]	8298	1			T14	1		T11	1241		T12	407
valid_sources[0x6f]	7889	1			T2	4		T11	370		T12	557
valid_sources[0x70]	7477	1			T11	887		T12	471		T13	625
valid_sources[0x71]	6438	1			T15	1		T11	114		T12	483
valid_sources[0x72]	6906	1			T49	1		T12	500		T13	813
valid_sources[0x73]	7933	1			T14	1		T11	1446		T12	579
valid_sources[0x74]	6222	1			T2	5		T14	1		T12	502
valid_sources[0x75]	7693	1			T15	2		T11	1067		T12	520
valid_sources[0x76]	8592	1			T14	2		T11	1847		T12	514
valid_sources[0x77]	9730	1			T14	1		T11	895		T12	424
valid_sources[0x78]	5955	1			T2	1		T14	2		T11	341
valid_sources[0x79]	8618	1			T2	3		T11	1778		T12	445
valid_sources[0x7a]	6884	1			T4	52		T12	493		T13	276
valid_sources[0x7b]	8246	1			T15	2		T11	935		T12	484
valid_sources[0x7c]	8034	1			T49	1		T12	554		T13	2034
valid_sources[0x7d]	7934	1			T16	2		T12	482		T13	1322
valid_sources[0x7e]	6319	1			T11	317		T12	451		T13	260
valid_sources[0x7f]	7703	1			T5	13		T14	4		T11	171
valid_sources[0x80]	7690	1			T3	1		T11	331		T12	501

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

479801

1

T1

6

T2

15

T3

6

values[0x0]

all_enables

biggest_size

714081

1

T11

49016

T12

45014

T13

97576

values[0x1]

all_enables

biggest_size

714441

1

T11

49001

T12

45224

T13

97570

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	141252	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1430292

1

T1

17

T2

28

T3

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	390380	1			T1	32		T2	64		T3	33
values[0x0]	545585	1			T6	6		T9	6		T22	4
values[0x1]	635579	1			T6	15		T9	3		T22	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	62927	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1508617

1

T1

20

T2

34

T3

18

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6704	1			T11	471		T12	356		T13	917
valid_sources[0x01]	6409	1			T11	415		T12	357		T13	856
valid_sources[0x02]	5903	1			T15	1		T11	467		T12	369
valid_sources[0x03]	6328	1			T15	1		T11	428		T12	344
valid_sources[0x04]	6832	1			T11	425		T12	363		T13	854
valid_sources[0x05]	6435	1			T2	1		T11	438		T12	396
valid_sources[0x06]	5423	1			T6	1		T11	402		T12	348
valid_sources[0x07]	5786	1			T11	413		T12	345		T13	896
valid_sources[0x08]	6785	1			T11	419		T12	390		T13	834
valid_sources[0x09]	5905	1			T5	1		T6	1		T11	454
valid_sources[0x0a]	6544	1			T2	1		T11	401		T49	1
valid_sources[0x0b]	6486	1			T11	425		T12	362		T13	878
valid_sources[0x0c]	6230	1			T11	446		T12	389		T13	854
valid_sources[0x0d]	6118	1			T1	2		T9	1		T11	445
valid_sources[0x0e]	6124	1			T11	420		T12	359		T13	873
valid_sources[0x0f]	6539	1			T11	444		T12	334		T13	822
valid_sources[0x10]	6406	1			T10	1		T11	345		T12	361
valid_sources[0x11]	6095	1			T11	426		T12	384		T13	813
valid_sources[0x12]	6464	1			T1	1		T5	2		T11	397
valid_sources[0x13]	5631	1			T5	1		T11	395		T12	322
valid_sources[0x14]	7334	1			T2	1		T5	3		T11	371
valid_sources[0x15]	6017	1			T2	2		T15	1		T11	395
valid_sources[0x16]	5906	1			T11	403		T12	356		T13	861
valid_sources[0x17]	6433	1			T10	1		T11	408		T12	364
valid_sources[0x18]	5548	1			T5	1		T15	1		T11	427
valid_sources[0x19]	5559	1			T11	439		T12	383		T13	877
valid_sources[0x1a]	6506	1			T5	3		T11	399		T12	375
valid_sources[0x1b]	6673	1			T10	1		T11	419		T12	392
valid_sources[0x1c]	6375	1			T2	1		T11	433		T12	336
valid_sources[0x1d]	6704	1			T1	1		T11	424		T12	367
valid_sources[0x1e]	6708	1			T6	1		T22	9		T11	405
valid_sources[0x1f]	5975	1			T11	381		T12	349		T35	1
valid_sources[0x20]	5984	1			T2	1		T10	1		T11	430
valid_sources[0x21]	6364	1			T1	1		T2	3		T11	412
valid_sources[0x22]	6236	1			T11	434		T49	1		T12	369
valid_sources[0x23]	6389	1			T2	1		T11	446		T12	363
valid_sources[0x24]	5739	1			T11	439		T12	329		T13	810
valid_sources[0x25]	5373	1			T11	446		T12	358		T13	837
valid_sources[0x26]	5793	1			T5	2		T10	1		T11	376
valid_sources[0x27]	5800	1			T15	2		T11	376		T12	387
valid_sources[0x28]	6232	1			T2	1		T11	396		T49	1
valid_sources[0x29]	5999	1			T11	431		T12	352		T35	1
valid_sources[0x2a]	5271	1			T5	3		T11	385		T49	1
valid_sources[0x2b]	6139	1			T1	8		T11	383		T12	354
valid_sources[0x2c]	6621	1			T1	1		T2	2		T7	1
valid_sources[0x2d]	6087	1			T5	3		T10	1		T15	2
valid_sources[0x2e]	5687	1			T11	420		T12	348		T13	854
valid_sources[0x2f]	5788	1			T15	2		T11	403		T12	342
valid_sources[0x30]	6222	1			T11	463		T12	371		T13	837
valid_sources[0x31]	6743	1			T11	378		T12	357		T13	862
valid_sources[0x32]	5992	1			T7	4		T15	1		T11	412
valid_sources[0x33]	6703	1			T10	1		T11	435		T12	334
valid_sources[0x34]	6205	1			T11	420		T12	375		T13	844
valid_sources[0x35]	5824	1			T5	3		T15	2		T11	418
valid_sources[0x36]	6258	1			T11	420		T12	375		T13	797
valid_sources[0x37]	6224	1			T11	406		T12	360		T13	825
valid_sources[0x38]	6237	1			T11	400		T12	394		T13	850
valid_sources[0x39]	6268	1			T2	1		T11	446		T12	349
valid_sources[0x3a]	5615	1			T15	1		T11	436		T12	376
valid_sources[0x3b]	5274	1			T11	373		T12	344		T13	828
valid_sources[0x3c]	5970	1			T11	377		T12	376		T13	860
valid_sources[0x3d]	5651	1			T1	1		T11	460		T12	326
valid_sources[0x3e]	6221	1			T11	452		T12	360		T13	834
valid_sources[0x3f]	5756	1			T7	3		T11	419		T12	337
valid_sources[0x40]	6248	1			T6	1		T11	452		T12	347
valid_sources[0x41]	6229	1			T11	417		T12	366		T13	843
valid_sources[0x42]	6295	1			T11	396		T21	1		T12	363
valid_sources[0x43]	6471	1			T5	1		T11	401		T49	1
valid_sources[0x44]	6706	1			T7	4		T11	400		T49	2
valid_sources[0x45]	6186	1			T1	1		T11	469		T12	369
valid_sources[0x46]	6596	1			T11	359		T12	361		T35	2
valid_sources[0x47]	6559	1			T5	1		T11	434		T12	362
valid_sources[0x48]	6393	1			T1	1		T5	5		T11	412
valid_sources[0x49]	6816	1			T11	410		T12	365		T13	863
valid_sources[0x4a]	5739	1			T10	1		T11	422		T49	1
valid_sources[0x4b]	7047	1			T10	1		T11	442		T12	353
valid_sources[0x4c]	5630	1			T15	1		T11	432		T12	387
valid_sources[0x4d]	6073	1			T15	2		T11	467		T12	357
valid_sources[0x4e]	6823	1			T5	1		T15	1		T56	8
valid_sources[0x4f]	5748	1			T2	2		T11	398		T12	318
valid_sources[0x50]	6502	1			T11	426		T12	362		T13	848
valid_sources[0x51]	5884	1			T1	2		T2	1		T11	405
valid_sources[0x52]	5650	1			T11	405		T12	376		T13	853
valid_sources[0x53]	6498	1			T11	458		T12	385		T13	848
valid_sources[0x54]	6277	1			T10	1		T11	455		T12	353
valid_sources[0x55]	6226	1			T8	1		T15	1		T11	392
valid_sources[0x56]	6503	1			T11	387		T49	1		T12	344
valid_sources[0x57]	5308	1			T11	386		T12	362		T13	842
valid_sources[0x58]	6500	1			T2	1		T11	395		T12	350
valid_sources[0x59]	6638	1			T11	407		T12	370		T13	851
valid_sources[0x5a]	5920	1			T11	417		T12	348		T13	821
valid_sources[0x5b]	6253	1			T11	394		T12	376		T13	911
valid_sources[0x5c]	6331	1			T5	3		T11	420		T12	369
valid_sources[0x5d]	5914	1			T2	1		T11	399		T12	366
valid_sources[0x5e]	5307	1			T11	403		T49	1		T12	354
valid_sources[0x5f]	5810	1			T11	394		T12	328		T35	1
valid_sources[0x60]	5800	1			T11	403		T12	313		T13	866
valid_sources[0x61]	5903	1			T11	417		T49	1		T12	344
valid_sources[0x62]	6219	1			T10	1		T11	426		T12	382
valid_sources[0x63]	6227	1			T5	2		T6	1		T11	401
valid_sources[0x64]	6318	1			T15	1		T11	413		T49	1
valid_sources[0x65]	5740	1			T2	1		T11	426		T12	382
valid_sources[0x66]	5369	1			T5	1		T11	402		T49	1
valid_sources[0x67]	4985	1			T1	1		T2	1		T11	394
valid_sources[0x68]	5431	1			T11	439		T12	389		T13	842
valid_sources[0x69]	6133	1			T10	1		T11	445		T12	368
valid_sources[0x6a]	6197	1			T2	1		T6	1		T11	426
valid_sources[0x6b]	6415	1			T2	1		T11	428		T12	387
valid_sources[0x6c]	5872	1			T11	438		T49	1		T12	397
valid_sources[0x6d]	6551	1			T11	454		T12	364		T13	844
valid_sources[0x6e]	5846	1			T1	1		T11	399		T12	348
valid_sources[0x6f]	5907	1			T2	4		T11	384		T12	362
valid_sources[0x70]	5484	1			T11	408		T12	375		T13	844
valid_sources[0x71]	6088	1			T11	426		T12	390		T13	892
valid_sources[0x72]	5495	1			T5	1		T11	420		T12	345
valid_sources[0x73]	6456	1			T11	374		T12	384		T13	816
valid_sources[0x74]	6113	1			T10	1		T15	1		T11	415
valid_sources[0x75]	5973	1			T11	442		T12	367		T13	848
valid_sources[0x76]	5683	1			T11	449		T12	348		T13	852
valid_sources[0x77]	5564	1			T9	2		T11	420		T12	377
valid_sources[0x78]	7046	1			T2	3		T11	416		T12	353
valid_sources[0x79]	6406	1			T2	1		T5	3		T15	1
valid_sources[0x7a]	6721	1			T5	4		T11	394		T12	388
valid_sources[0x7b]	6235	1			T11	414		T12	357		T13	880
valid_sources[0x7c]	6199	1			T2	1		T11	406		T12	351
valid_sources[0x7d]	6461	1			T11	433		T12	378		T13	857
valid_sources[0x7e]	7444	1			T9	2		T11	456		T12	339
valid_sources[0x7f]	6171	1			T2	1		T11	459		T12	336
valid_sources[0x80]	6976	1			T11	396		T12	336		T13	833

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

359944

1

T1

17

T2

28

T3

13

values[0x0]

all_enables

biggest_size

534512

1

T6

2

T9

4

T22

1

values[0x1]

all_enables

biggest_size

535836

1

T6

2

T9

1

T22

1