Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3479301

1

T1

68

T2

130

T4

251

full_word

2226609

1

T1

6

T2

15

T3

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	5705590	1			T1	74		T2	145		T3	4
auto[TlIntgErrCmd]	122	1			T51	10		T52	3		T53	8
auto[TlIntgErrData]	107	1			T51	6		T52	4		T53	6
auto[TlIntgErrBoth]	91	1			T51	4		T52	3		T53	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

902997

1

T1

74

T2

145

T3

4

auto[1]

4802913

1

T11

336007

T12

303461

T13

671872

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	376942	1			T1	68		T2	130		T4	251
auto[TlIntgErrNone]	partial	auto[1]	3102065	1			T11	218919		T12	195966		T13	438148
auto[TlIntgErrNone]	full_word	auto[0]	525912	1			T1	6		T2	15		T3	4
auto[TlIntgErrNone]	full_word	auto[1]	1700671	1			T11	117088		T12	107495		T13	233724
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T51	2		T53	1		T98	2
auto[TlIntgErrCmd]	partial	auto[1]	68	1			T51	5		T52	3		T53	6
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T51	1		T102	1		T106	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T51	2		T53	1		T107	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T51	2		T53	2		T98	3
auto[TlIntgErrData]	partial	auto[1]	49	1			T51	4		T52	2		T53	4
auto[TlIntgErrData]	full_word	auto[0]	6	1			T52	2		T98	1		T102	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T108	1		T109	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T51	1		T52	1		T53	1
auto[TlIntgErrBoth]	partial	auto[1]	45	1			T51	3		T52	1		T53	5
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T100	1		T110	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T52	1		T111	1		T107	1