Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	68613	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1510200

1

T1

8

T4

7

T5

39616

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	418314	1			T1	66		T4	71		T5	10413
values[0x0]	568656	1			T5	14874		T8	75832		T11	14905
values[0x1]	591843	1			T5	15532		T8	79723		T11	15170

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34927	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1543886

1

T1

33

T4

42

T5

40155

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5513	1			T5	159		T7	1		T8	743
valid_sources[0x01]	5085	1			T5	160		T8	858		T39	1
valid_sources[0x02]	5939	1			T5	180		T7	1		T8	831
valid_sources[0x03]	6119	1			T5	141		T7	1		T8	881
valid_sources[0x04]	5123	1			T5	166		T8	870		T38	2
valid_sources[0x05]	5186	1			T5	173		T7	2		T8	776
valid_sources[0x06]	6184	1			T5	167		T7	1		T8	714
valid_sources[0x07]	5612	1			T5	155		T8	739		T38	4
valid_sources[0x08]	5408	1			T1	1		T5	144		T8	766
valid_sources[0x09]	5552	1			T5	135		T7	2		T8	904
valid_sources[0x0a]	8368	1			T1	1		T5	141		T7	2
valid_sources[0x0b]	5622	1			T4	1		T5	150		T7	1
valid_sources[0x0c]	5835	1			T4	1		T5	128		T8	828
valid_sources[0x0d]	7353	1			T1	1		T5	124		T7	2
valid_sources[0x0e]	5852	1			T5	137		T7	2		T8	776
valid_sources[0x0f]	6061	1			T1	1		T5	185		T8	854
valid_sources[0x10]	5843	1			T4	4		T5	173		T6	98
valid_sources[0x11]	6488	1			T5	161		T7	3		T8	833
valid_sources[0x12]	6281	1			T1	1		T5	165		T8	792
valid_sources[0x13]	6174	1			T1	1		T5	137		T8	690
valid_sources[0x14]	5063	1			T5	158		T8	825		T15	2
valid_sources[0x15]	5385	1			T5	146		T8	823		T38	1
valid_sources[0x16]	6361	1			T1	1		T5	174		T7	1
valid_sources[0x17]	6537	1			T5	153		T8	809		T38	1
valid_sources[0x18]	4955	1			T1	1		T5	158		T7	1
valid_sources[0x19]	7317	1			T5	171		T8	904		T98	1
valid_sources[0x1a]	5275	1			T1	1		T5	151		T7	1
valid_sources[0x1b]	5236	1			T5	170		T8	777		T38	2
valid_sources[0x1c]	5037	1			T5	131		T8	863		T15	5
valid_sources[0x1d]	5974	1			T1	1		T5	152		T8	834
valid_sources[0x1e]	6023	1			T1	1		T5	166		T6	16
valid_sources[0x1f]	7402	1			T5	148		T8	780		T14	7
valid_sources[0x20]	5744	1			T5	148		T7	1		T8	745
valid_sources[0x21]	6221	1			T4	14		T5	147		T7	6
valid_sources[0x22]	6726	1			T5	156		T8	827		T14	7
valid_sources[0x23]	6659	1			T5	170		T7	1		T8	851
valid_sources[0x24]	6976	1			T5	159		T8	810		T38	1
valid_sources[0x25]	7166	1			T5	153		T8	808		T15	2
valid_sources[0x26]	5693	1			T5	151		T8	880		T38	3
valid_sources[0x27]	6368	1			T5	176		T8	754		T38	1
valid_sources[0x28]	5353	1			T5	164		T8	818		T38	1
valid_sources[0x29]	7336	1			T5	169		T7	1		T8	836
valid_sources[0x2a]	6245	1			T5	173		T8	875		T98	1
valid_sources[0x2b]	6365	1			T5	141		T8	804		T38	2
valid_sources[0x2c]	8024	1			T4	4		T5	155		T8	743
valid_sources[0x2d]	7027	1			T5	214		T8	874		T38	2
valid_sources[0x2e]	4660	1			T5	150		T7	1		T8	762
valid_sources[0x2f]	5931	1			T5	148		T8	818		T38	2
valid_sources[0x30]	6245	1			T5	163		T7	1		T8	786
valid_sources[0x31]	5202	1			T5	126		T7	1		T8	811
valid_sources[0x32]	6685	1			T5	154		T7	3		T8	863
valid_sources[0x33]	7038	1			T5	125		T8	841		T38	1
valid_sources[0x34]	7080	1			T5	160		T7	6		T8	816
valid_sources[0x35]	5683	1			T5	160		T8	847		T99	2
valid_sources[0x36]	5895	1			T5	155		T7	3		T8	822
valid_sources[0x37]	7631	1			T5	132		T8	802		T38	1
valid_sources[0x38]	6939	1			T5	130		T8	776		T38	1
valid_sources[0x39]	7214	1			T4	7		T5	174		T8	896
valid_sources[0x3a]	5767	1			T5	155		T7	1		T8	720
valid_sources[0x3b]	6267	1			T5	154		T8	854		T39	1
valid_sources[0x3c]	5453	1			T1	2		T5	161		T8	721
valid_sources[0x3d]	7369	1			T5	170		T7	3		T8	745
valid_sources[0x3e]	4956	1			T5	160		T7	3		T8	743
valid_sources[0x3f]	8601	1			T1	1		T5	147		T7	5
valid_sources[0x40]	6307	1			T5	171		T7	6		T8	851
valid_sources[0x41]	7983	1			T5	152		T8	833		T38	2
valid_sources[0x42]	5355	1			T4	1		T5	188		T7	2
valid_sources[0x43]	5612	1			T5	196		T8	725		T98	3
valid_sources[0x44]	5164	1			T5	139		T8	812		T38	1
valid_sources[0x45]	5755	1			T1	1		T4	6		T5	176
valid_sources[0x46]	5323	1			T5	172		T7	2		T8	915
valid_sources[0x47]	5163	1			T1	1		T5	169		T8	783
valid_sources[0x48]	5817	1			T5	160		T8	715		T98	1
valid_sources[0x49]	6095	1			T1	1		T5	151		T7	2
valid_sources[0x4a]	5827	1			T5	158		T7	5		T8	832
valid_sources[0x4b]	5785	1			T5	167		T7	1		T8	797
valid_sources[0x4c]	6027	1			T5	164		T8	710		T99	1
valid_sources[0x4d]	5512	1			T5	163		T7	5		T8	786
valid_sources[0x4e]	7351	1			T5	152		T7	2		T8	837
valid_sources[0x4f]	7474	1			T4	9		T5	162		T7	2
valid_sources[0x50]	5641	1			T5	166		T7	1		T8	830
valid_sources[0x51]	5217	1			T5	174		T6	39		T7	1
valid_sources[0x52]	5140	1			T5	163		T8	788		T38	1
valid_sources[0x53]	5906	1			T5	142		T8	870		T33	1
valid_sources[0x54]	4902	1			T5	175		T7	2		T8	781
valid_sources[0x55]	5331	1			T1	1		T5	157		T7	4
valid_sources[0x56]	4858	1			T5	172		T7	5		T8	795
valid_sources[0x57]	6703	1			T5	162		T8	804		T38	2
valid_sources[0x58]	5249	1			T5	163		T7	5		T8	730
valid_sources[0x59]	7746	1			T5	159		T7	9		T8	711
valid_sources[0x5a]	7455	1			T5	162		T8	828		T14	7
valid_sources[0x5b]	6374	1			T5	170		T7	2		T8	787
valid_sources[0x5c]	6749	1			T1	1		T5	161		T8	811
valid_sources[0x5d]	6906	1			T1	1		T5	167		T8	754
valid_sources[0x5e]	5432	1			T1	1		T5	154		T8	780
valid_sources[0x5f]	6032	1			T5	168		T8	850		T11	155
valid_sources[0x60]	6393	1			T1	1		T5	169		T8	870
valid_sources[0x61]	5885	1			T5	175		T8	850		T39	2
valid_sources[0x62]	6831	1			T5	170		T7	1		T8	783
valid_sources[0x63]	5732	1			T5	168		T7	2		T8	819
valid_sources[0x64]	6387	1			T1	2		T5	148		T8	830
valid_sources[0x65]	5898	1			T5	171		T8	848		T38	3
valid_sources[0x66]	5246	1			T5	167		T8	884		T98	1
valid_sources[0x67]	5722	1			T5	153		T8	840		T38	1
valid_sources[0x68]	5022	1			T5	171		T7	5		T8	751
valid_sources[0x69]	6366	1			T1	1		T5	164		T8	879
valid_sources[0x6a]	6545	1			T5	181		T7	1		T8	856
valid_sources[0x6b]	6808	1			T5	155		T7	7		T8	880
valid_sources[0x6c]	4913	1			T5	150		T7	1		T8	788
valid_sources[0x6d]	5842	1			T5	171		T7	1		T8	813
valid_sources[0x6e]	6738	1			T1	1		T5	178		T7	1
valid_sources[0x6f]	8063	1			T5	181		T7	1		T8	800
valid_sources[0x70]	5456	1			T1	1		T4	12		T5	152
valid_sources[0x71]	5257	1			T1	1		T5	142		T6	20
valid_sources[0x72]	6273	1			T5	167		T7	2		T8	876
valid_sources[0x73]	6350	1			T5	171		T7	2		T8	761
valid_sources[0x74]	7596	1			T1	1		T5	130		T7	1
valid_sources[0x75]	6440	1			T5	162		T7	1		T8	798
valid_sources[0x76]	5917	1			T5	173		T7	5		T8	804
valid_sources[0x77]	6093	1			T5	169		T8	858		T38	5
valid_sources[0x78]	5687	1			T5	153		T7	3		T8	849
valid_sources[0x79]	5559	1			T1	1		T5	146		T7	1
valid_sources[0x7a]	6140	1			T5	161		T7	6		T8	781
valid_sources[0x7b]	5831	1			T5	184		T8	772		T38	1
valid_sources[0x7c]	5445	1			T5	157		T7	2		T8	820
valid_sources[0x7d]	6327	1			T1	1		T5	174		T8	805
valid_sources[0x7e]	6389	1			T1	1		T5	160		T7	1
valid_sources[0x7f]	6460	1			T5	150		T8	817		T38	1
valid_sources[0x80]	5046	1			T5	147		T7	1		T8	866

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

380558

1

T1

8

T4

7

T5

10021

values[0x0]

all_enables

biggest_size

563694

1

T5

14761

T8

75155

T11

14785

values[0x1]

all_enables

biggest_size

565948

1

T5

14834

T8

76280

T11

14584

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	115796	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1160137

1

T1

18

T3

2

T4

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	320436	1			T1	32		T2	1		T4	32
values[0x0]	442587	1			T3	4		T5	12168		T8	59375
values[0x1]	512910	1			T3	2		T5	13922		T8	68933

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	52410	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1223523

1

T1

20

T2

1

T3

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4952	1			T5	117		T8	669		T99	2
valid_sources[0x01]	4766	1			T5	110		T8	574		T15	2
valid_sources[0x02]	5658	1			T4	1		T5	144		T8	673
valid_sources[0x03]	4720	1			T5	125		T8	643		T11	120
valid_sources[0x04]	4955	1			T5	133		T8	647		T11	126
valid_sources[0x05]	4789	1			T5	154		T8	655		T16	1
valid_sources[0x06]	4479	1			T5	136		T8	738		T9	21
valid_sources[0x07]	5059	1			T5	120		T8	620		T11	122
valid_sources[0x08]	4910	1			T5	129		T8	585		T16	2
valid_sources[0x09]	5367	1			T4	1		T5	132		T8	595
valid_sources[0x0a]	5696	1			T5	134		T8	680		T99	1
valid_sources[0x0b]	4592	1			T5	142		T8	598		T11	132
valid_sources[0x0c]	4846	1			T5	139		T8	636		T11	112
valid_sources[0x0d]	6770	1			T5	120		T8	670		T99	2
valid_sources[0x0e]	5273	1			T5	159		T8	738		T99	2
valid_sources[0x0f]	4705	1			T5	155		T8	710		T99	4
valid_sources[0x10]	5617	1			T5	119		T8	725		T99	1
valid_sources[0x11]	5049	1			T5	139		T8	687		T16	1
valid_sources[0x12]	4741	1			T5	143		T8	734		T11	165
valid_sources[0x13]	5175	1			T1	4		T5	119		T8	608
valid_sources[0x14]	4822	1			T5	126		T8	640		T11	99
valid_sources[0x15]	4408	1			T5	126		T8	589		T11	114
valid_sources[0x16]	5065	1			T5	127		T8	669		T11	137
valid_sources[0x17]	4344	1			T5	143		T8	657		T99	1
valid_sources[0x18]	5125	1			T5	136		T8	673		T11	102
valid_sources[0x19]	4724	1			T5	142		T8	685		T11	102
valid_sources[0x1a]	4887	1			T2	1		T5	128		T8	620
valid_sources[0x1b]	4986	1			T5	121		T8	671		T11	131
valid_sources[0x1c]	5449	1			T5	118		T8	737		T11	123
valid_sources[0x1d]	4352	1			T5	123		T8	609		T11	131
valid_sources[0x1e]	4537	1			T5	132		T8	723		T11	118
valid_sources[0x1f]	5389	1			T4	2		T5	141		T8	643
valid_sources[0x20]	4788	1			T5	130		T8	639		T11	125
valid_sources[0x21]	5277	1			T5	126		T8	636		T39	32
valid_sources[0x22]	5544	1			T5	127		T8	637		T11	111
valid_sources[0x23]	4657	1			T5	131		T8	633		T11	93
valid_sources[0x24]	5234	1			T1	3		T5	140		T8	651
valid_sources[0x25]	5133	1			T5	157		T8	661		T11	134
valid_sources[0x26]	5202	1			T1	1		T5	134		T8	659
valid_sources[0x27]	5182	1			T5	128		T8	614		T11	123
valid_sources[0x28]	5134	1			T5	156		T8	684		T34	1
valid_sources[0x29]	5758	1			T5	131		T8	718		T99	1
valid_sources[0x2a]	4423	1			T5	130		T8	649		T11	98
valid_sources[0x2b]	4762	1			T5	128		T8	724		T34	1
valid_sources[0x2c]	4734	1			T5	129		T8	717		T99	1
valid_sources[0x2d]	4665	1			T5	138		T8	732		T99	1
valid_sources[0x2e]	5344	1			T5	154		T8	661		T99	2
valid_sources[0x2f]	5890	1			T5	139		T8	722		T99	3
valid_sources[0x30]	4652	1			T5	128		T8	642		T16	2
valid_sources[0x31]	4756	1			T5	136		T8	687		T16	1
valid_sources[0x32]	4378	1			T5	129		T8	667		T11	105
valid_sources[0x33]	4555	1			T5	135		T8	702		T11	103
valid_sources[0x34]	4246	1			T5	127		T8	692		T99	1
valid_sources[0x35]	4861	1			T5	133		T8	737		T99	1
valid_sources[0x36]	5704	1			T5	137		T8	631		T99	1
valid_sources[0x37]	4436	1			T5	141		T8	675		T33	1
valid_sources[0x38]	4830	1			T5	106		T8	638		T10	2
valid_sources[0x39]	4866	1			T5	123		T8	750		T10	1
valid_sources[0x3a]	4863	1			T5	125		T8	657		T34	1
valid_sources[0x3b]	4001	1			T5	167		T8	690		T11	123
valid_sources[0x3c]	4876	1			T5	131		T8	684		T99	2
valid_sources[0x3d]	4766	1			T5	151		T8	696		T11	96
valid_sources[0x3e]	5244	1			T5	140		T8	673		T14	32
valid_sources[0x3f]	4918	1			T5	133		T8	640		T11	72
valid_sources[0x40]	4969	1			T5	130		T8	660		T15	4
valid_sources[0x41]	5043	1			T5	134		T8	659		T99	1
valid_sources[0x42]	5094	1			T5	136		T8	706		T11	125
valid_sources[0x43]	5287	1			T5	129		T8	672		T11	126
valid_sources[0x44]	4508	1			T5	149		T8	721		T99	2
valid_sources[0x45]	4791	1			T5	161		T8	728		T11	120
valid_sources[0x46]	4736	1			T5	141		T8	728		T10	3
valid_sources[0x47]	5110	1			T5	128		T8	660		T33	1
valid_sources[0x48]	5260	1			T1	12		T5	115		T8	726
valid_sources[0x49]	5274	1			T4	1		T5	131		T8	673
valid_sources[0x4a]	4887	1			T1	6		T5	125		T8	579
valid_sources[0x4b]	4358	1			T5	129		T8	647		T99	1
valid_sources[0x4c]	4703	1			T5	129		T8	672		T11	110
valid_sources[0x4d]	5347	1			T5	126		T8	670		T11	129
valid_sources[0x4e]	5093	1			T5	127		T8	694		T33	1
valid_sources[0x4f]	4926	1			T5	139		T8	638		T11	108
valid_sources[0x50]	6147	1			T5	135		T8	751		T99	2
valid_sources[0x51]	5305	1			T4	1		T5	141		T8	685
valid_sources[0x52]	4255	1			T4	1		T5	110		T8	675
valid_sources[0x53]	5334	1			T5	157		T8	640		T15	1
valid_sources[0x54]	5118	1			T5	142		T8	717		T11	160
valid_sources[0x55]	4815	1			T5	125		T8	607		T16	1
valid_sources[0x56]	5070	1			T5	132		T8	667		T11	107
valid_sources[0x57]	5273	1			T5	132		T8	628		T11	126
valid_sources[0x58]	4216	1			T4	1		T5	141		T8	667
valid_sources[0x59]	5199	1			T5	138		T8	697		T11	146
valid_sources[0x5a]	5946	1			T5	127		T8	692		T34	1
valid_sources[0x5b]	4984	1			T5	133		T8	708		T33	1
valid_sources[0x5c]	4919	1			T5	118		T8	692		T34	1
valid_sources[0x5d]	4532	1			T5	121		T8	682		T99	1
valid_sources[0x5e]	5374	1			T5	135		T8	669		T99	1
valid_sources[0x5f]	5261	1			T4	1		T5	127		T8	696
valid_sources[0x60]	4519	1			T5	147		T8	598		T11	119
valid_sources[0x61]	5226	1			T5	138		T8	627		T15	2
valid_sources[0x62]	4793	1			T5	141		T8	714		T11	94
valid_sources[0x63]	4959	1			T5	143		T8	608		T11	95
valid_sources[0x64]	5332	1			T5	148		T8	682		T11	115
valid_sources[0x65]	4707	1			T5	129		T8	670		T33	1
valid_sources[0x66]	5621	1			T5	148		T8	656		T34	2
valid_sources[0x67]	4976	1			T4	1		T5	131		T8	691
valid_sources[0x68]	4747	1			T4	1		T5	160		T8	646
valid_sources[0x69]	4993	1			T5	128		T8	729		T99	1
valid_sources[0x6a]	5099	1			T5	124		T6	96		T8	632
valid_sources[0x6b]	4448	1			T5	147		T8	690		T34	1
valid_sources[0x6c]	5630	1			T5	145		T8	651		T99	1
valid_sources[0x6d]	5192	1			T5	160		T8	706		T11	97
valid_sources[0x6e]	4608	1			T5	144		T8	662		T11	103
valid_sources[0x6f]	5013	1			T4	1		T5	123		T8	686
valid_sources[0x70]	5441	1			T5	151		T8	646		T34	1
valid_sources[0x71]	5167	1			T5	133		T8	717		T11	111
valid_sources[0x72]	5273	1			T5	137		T8	647		T99	1
valid_sources[0x73]	5079	1			T5	160		T8	625		T11	117
valid_sources[0x74]	5358	1			T5	117		T8	618		T16	1
valid_sources[0x75]	4559	1			T5	149		T8	627		T99	1
valid_sources[0x76]	5042	1			T5	132		T8	666		T11	128
valid_sources[0x77]	5800	1			T5	125		T8	638		T11	150
valid_sources[0x78]	4694	1			T5	106		T8	660		T11	100
valid_sources[0x79]	5206	1			T5	136		T8	658		T33	1
valid_sources[0x7a]	4704	1			T4	1		T5	163		T8	636
valid_sources[0x7b]	5374	1			T5	130		T8	697		T11	116
valid_sources[0x7c]	4970	1			T5	153		T8	632		T34	1
valid_sources[0x7d]	5448	1			T5	129		T8	662		T11	132
valid_sources[0x7e]	5113	1			T1	1		T5	143		T8	657
valid_sources[0x7f]	4409	1			T5	131		T8	618		T99	1
valid_sources[0x80]	4660	1			T5	121		T8	636		T11	139

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

293580

1

T1

18

T4

16

T5

8060

values[0x0]

all_enables

biggest_size

433528

1

T3

2

T5

11934

T8

58193

values[0x1]

all_enables

biggest_size

433029

1

T5

11838

T8

57858

T11

10599