Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2759281

1

T1

58

T4

64

T5

70817

full_word

1762386

1

T1

8

T4

7

T5

46137

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4521397	1			T1	66		T4	71		T5	116954
auto[TlIntgErrCmd]	89	1			T51	3		T52	7		T53	4
auto[TlIntgErrData]	76	1			T51	5		T52	5		T53	4
auto[TlIntgErrBoth]	105	1			T51	2		T52	8		T53	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

722714

1

T1

66

T4

71

T5

18026

auto[1]

3798953

1

T5

98928

T8

515395

T11

92450

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	305302	1			T1	58		T4	64		T5	7071
auto[TlIntgErrNone]	partial	auto[1]	2453733	1			T5	63746		T8	334394		T11	57983
auto[TlIntgErrNone]	full_word	auto[0]	417289	1			T1	8		T4	7		T5	10955
auto[TlIntgErrNone]	full_word	auto[1]	1345073	1			T5	35182		T8	181001		T11	34467
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T51	2		T52	3		T53	1
auto[TlIntgErrCmd]	partial	auto[1]	37	1			T52	3		T53	3		T105	6
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T110	2		T112	1		T113	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T51	1		T52	1		T105	1
auto[TlIntgErrData]	partial	auto[0]	30	1			T51	4		T52	1		T53	2
auto[TlIntgErrData]	partial	auto[1]	41	1			T51	1		T52	3		T53	2
auto[TlIntgErrData]	full_word	auto[0]	1	1			T113	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1			T52	1		T105	1		T112	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T51	2		T52	5		T53	2
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T52	3		T105	1		T114	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T106	1		T111	1		T107	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T106	1		T115	1		T111	1