Unified Coverage Report :: Group :: tb.dut.u_rom_ctrl_cov_if::rom_ctrl_tlul_cg

Group : tb.dut.u_rom_ctrl_cov_if::rom_ctrl_tlul_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
87.50	87.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rom_ctrl_cov_0/rom_ctrl_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
rom_ctrl_tlul_cg	87.50	1	100	1	64	64

---

Group Instance : rom_ctrl_tlul_cg
Comment: TLUL interface behaviors

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
87.50	1	100	1	64	64

---

Summary for Group Instance rom_ctrl_tlul_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	1	7	87.50

Variables for Group Instance rom_ctrl_tlul_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regs_req_check	3	0	3	100.00	100	1	1	0
cp_rom_invalid_condition	2	1	1	50.00	100	1	1	0
cp_rom_req_check	3	0	3	100.00	100	1	1	0

Summary for Variable cp_regs_req_check

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_regs_req_check

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
req_after_done	1739200	1			T7	64		T8	45043		T10	48
req_and_done	3	1			T51	1		T108	1		T109	1
req_before_done	6	1			T51	1		T69	3		T70	1

---

Summary for Variable cp_rom_invalid_condition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for cp_rom_invalid_condition

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
check_invalid	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

check_valid

85406436

1

T1

49540

T2

24732

T3

49502

---

Summary for Variable cp_rom_req_check

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rom_req_check

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
req_after_done	1931807	1			T4	5		T6	2		T7	132
req_and_done	62	1			T4	1		T6	1		T11	1
req_before_done	131	1			T7	2		T8	4		T10	2