Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	47184	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1346158

1

T4

13

T6

6

T7

19

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	356852	1			T4	204		T6	113		T7	146
values[0x0]	508847	1			T8	7860		T11	39668		T14	78546
values[0x1]	527643	1			T8	8212		T11	41423		T14	81620

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	24925	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1368417

1

T4

114

T6

61

T7

81

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6538	1			T8	77		T11	413		T13	7
valid_sources[0x01]	4514	1			T7	4		T8	94		T11	420
valid_sources[0x02]	5028	1			T8	76		T10	1		T11	431
valid_sources[0x03]	5036	1			T6	1		T8	90		T10	1
valid_sources[0x04]	6704	1			T8	84		T11	398		T13	1
valid_sources[0x05]	5172	1			T8	85		T10	1		T11	407
valid_sources[0x06]	5863	1			T8	84		T11	456		T13	1
valid_sources[0x07]	5248	1			T8	90		T10	2		T11	465
valid_sources[0x08]	4842	1			T6	1		T8	95		T10	3
valid_sources[0x09]	6527	1			T6	2		T8	78		T11	385
valid_sources[0x0a]	4708	1			T8	89		T11	399		T14	316
valid_sources[0x0b]	5625	1			T8	108		T11	450		T14	847
valid_sources[0x0c]	4636	1			T6	1		T8	85		T11	409
valid_sources[0x0d]	5741	1			T7	4		T8	85		T10	1
valid_sources[0x0e]	5061	1			T7	6		T8	68		T11	509
valid_sources[0x0f]	5851	1			T8	67		T10	2		T11	412
valid_sources[0x10]	5828	1			T6	1		T8	85		T11	429
valid_sources[0x11]	7577	1			T6	2		T8	83		T11	422
valid_sources[0x12]	5685	1			T6	3		T7	4		T8	80
valid_sources[0x13]	6024	1			T8	104		T11	329		T13	10
valid_sources[0x14]	5805	1			T8	85		T11	422		T14	310
valid_sources[0x15]	5348	1			T6	1		T8	98		T11	459
valid_sources[0x16]	4497	1			T8	82		T11	419		T14	126
valid_sources[0x17]	5049	1			T8	95		T11	448		T14	548
valid_sources[0x18]	4637	1			T6	1		T8	77		T11	530
valid_sources[0x19]	5541	1			T7	5		T8	93		T11	367
valid_sources[0x1a]	5385	1			T8	76		T11	450		T14	1058
valid_sources[0x1b]	5424	1			T8	70		T11	439		T13	7
valid_sources[0x1c]	5156	1			T8	91		T10	3		T11	439
valid_sources[0x1d]	4831	1			T8	78		T10	3		T11	434
valid_sources[0x1e]	5393	1			T8	75		T11	464		T14	553
valid_sources[0x1f]	5112	1			T6	1		T8	86		T11	399
valid_sources[0x20]	4804	1			T6	1		T8	84		T11	413
valid_sources[0x21]	5906	1			T4	27		T7	2		T8	108
valid_sources[0x22]	5159	1			T8	64		T11	413		T14	474
valid_sources[0x23]	4922	1			T8	89		T11	349		T14	264
valid_sources[0x24]	4990	1			T8	77		T10	1		T11	443
valid_sources[0x25]	5718	1			T8	69		T11	351		T14	970
valid_sources[0x26]	4798	1			T8	89		T11	447		T14	362
valid_sources[0x27]	5389	1			T8	90		T11	377		T14	1151
valid_sources[0x28]	5513	1			T8	77		T11	479		T14	802
valid_sources[0x29]	4584	1			T8	78		T10	1		T11	412
valid_sources[0x2a]	5568	1			T8	88		T11	360		T13	5
valid_sources[0x2b]	6096	1			T8	86		T10	1		T11	496
valid_sources[0x2c]	5013	1			T8	92		T11	472		T13	14
valid_sources[0x2d]	5438	1			T8	88		T11	374		T14	316
valid_sources[0x2e]	6267	1			T7	8		T8	100		T11	427
valid_sources[0x2f]	5810	1			T6	2		T8	106		T11	431
valid_sources[0x30]	5482	1			T8	97		T11	373		T14	1132
valid_sources[0x31]	5001	1			T8	110		T11	398		T14	556
valid_sources[0x32]	5213	1			T8	91		T11	384		T13	2
valid_sources[0x33]	5212	1			T4	33		T6	4		T8	77
valid_sources[0x34]	5914	1			T6	1		T8	73		T10	1
valid_sources[0x35]	5006	1			T7	3		T8	63		T10	1
valid_sources[0x36]	5378	1			T6	1		T7	1		T8	90
valid_sources[0x37]	4585	1			T6	1		T8	88		T11	483
valid_sources[0x38]	4518	1			T8	73		T11	320		T14	150
valid_sources[0x39]	4906	1			T8	93		T11	384		T13	6
valid_sources[0x3a]	5875	1			T8	81		T11	423		T14	1239
valid_sources[0x3b]	5627	1			T8	92		T11	347		T14	1174
valid_sources[0x3c]	5442	1			T6	2		T8	75		T11	414
valid_sources[0x3d]	5273	1			T8	74		T11	502		T13	6
valid_sources[0x3e]	5734	1			T8	93		T11	367		T14	1226
valid_sources[0x3f]	4583	1			T8	83		T11	359		T13	1
valid_sources[0x40]	5099	1			T6	1		T7	6		T8	65
valid_sources[0x41]	7476	1			T8	76		T11	411		T14	3133
valid_sources[0x42]	5212	1			T6	2		T8	72		T11	368
valid_sources[0x43]	6672	1			T7	2		T8	100		T11	388
valid_sources[0x44]	7049	1			T8	81		T11	460		T13	1
valid_sources[0x45]	5406	1			T8	92		T10	3		T11	463
valid_sources[0x46]	6332	1			T6	1		T8	96		T11	416
valid_sources[0x47]	5543	1			T7	5		T8	78		T11	447
valid_sources[0x48]	5503	1			T4	42		T6	1		T8	108
valid_sources[0x49]	5887	1			T6	1		T8	80		T11	399
valid_sources[0x4a]	6412	1			T8	80		T11	425		T14	1480
valid_sources[0x4b]	7027	1			T8	85		T10	1		T11	429
valid_sources[0x4c]	5191	1			T6	1		T8	106		T11	468
valid_sources[0x4d]	4383	1			T8	105		T11	391		T63	69
valid_sources[0x4e]	6193	1			T6	1		T8	96		T11	379
valid_sources[0x4f]	6553	1			T4	15		T8	80		T11	387
valid_sources[0x50]	5735	1			T7	3		T8	118		T10	1
valid_sources[0x51]	5654	1			T8	59		T10	4		T11	362
valid_sources[0x52]	5386	1			T8	80		T11	462		T14	268
valid_sources[0x53]	5576	1			T8	92		T11	439		T14	918
valid_sources[0x54]	5474	1			T6	2		T7	3		T8	72
valid_sources[0x55]	4982	1			T8	95		T11	460		T14	468
valid_sources[0x56]	4723	1			T8	98		T10	2		T11	410
valid_sources[0x57]	4682	1			T6	2		T8	81		T10	2
valid_sources[0x58]	4909	1			T6	1		T8	81		T11	420
valid_sources[0x59]	4525	1			T6	1		T8	102		T11	428
valid_sources[0x5a]	4679	1			T8	83		T11	471		T13	6
valid_sources[0x5b]	4921	1			T8	88		T11	341		T13	2
valid_sources[0x5c]	4829	1			T8	117		T11	441		T14	457
valid_sources[0x5d]	4530	1			T8	68		T11	417		T14	15
valid_sources[0x5e]	6182	1			T8	94		T11	401		T14	1535
valid_sources[0x5f]	6047	1			T6	1		T8	61		T11	418
valid_sources[0x60]	4704	1			T8	75		T11	390		T13	8
valid_sources[0x61]	5590	1			T6	2		T8	78		T11	467
valid_sources[0x62]	5390	1			T8	82		T11	376		T14	981
valid_sources[0x63]	5497	1			T8	91		T11	481		T14	988
valid_sources[0x64]	4939	1			T8	87		T11	421		T14	108
valid_sources[0x65]	5463	1			T8	85		T11	401		T14	939
valid_sources[0x66]	5416	1			T8	90		T11	397		T13	1
valid_sources[0x67]	5044	1			T8	71		T11	435		T14	650
valid_sources[0x68]	5219	1			T8	76		T11	415		T13	6
valid_sources[0x69]	5165	1			T8	90		T11	436		T14	500
valid_sources[0x6a]	5945	1			T8	66		T10	1		T11	448
valid_sources[0x6b]	6057	1			T8	104		T11	430		T14	1709
valid_sources[0x6c]	5740	1			T8	90		T10	1		T11	437
valid_sources[0x6d]	5204	1			T8	86		T11	404		T14	870
valid_sources[0x6e]	5734	1			T6	1		T7	4		T8	73
valid_sources[0x6f]	5912	1			T6	1		T8	91		T11	392
valid_sources[0x70]	4706	1			T8	116		T11	392		T13	3
valid_sources[0x71]	5862	1			T8	78		T11	353		T14	1370
valid_sources[0x72]	5886	1			T8	85		T10	1		T11	474
valid_sources[0x73]	6861	1			T8	82		T11	409		T14	2485
valid_sources[0x74]	5467	1			T8	105		T11	464		T13	5
valid_sources[0x75]	8054	1			T6	1		T8	72		T10	1
valid_sources[0x76]	5878	1			T7	2		T8	82		T11	417
valid_sources[0x77]	5016	1			T6	1		T8	92		T10	2
valid_sources[0x78]	4543	1			T6	1		T8	72		T11	433
valid_sources[0x79]	5298	1			T8	81		T10	1		T11	457
valid_sources[0x7a]	5037	1			T8	87		T11	437		T14	554
valid_sources[0x7b]	5703	1			T6	2		T8	89		T10	1
valid_sources[0x7c]	5276	1			T8	91		T11	404		T13	2
valid_sources[0x7d]	5852	1			T8	89		T10	2		T11	408
valid_sources[0x7e]	5626	1			T8	75		T11	404		T14	631
valid_sources[0x7f]	5654	1			T6	2		T8	77		T11	422
valid_sources[0x80]	4626	1			T8	103		T11	453		T13	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

337225

1

T4

13

T6

6

T7

19

values[0x0]

all_enables

biggest_size

504340

1

T8

7794

T11

39319

T14

77855

values[0x1]

all_enables

biggest_size

504593

1

T8

7852

T11

39629

T14

78127

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	100052	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1027565

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	278245	1			T1	1		T3	1		T5	1
values[0x0]	393340	1			T2	4		T8	6490		T11	31169
values[0x1]	456032	1			T2	5		T8	7500		T11	36121

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44449	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1083168

1

T1

1

T2

2

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4413	1			T7	1		T8	69		T11	345
valid_sources[0x01]	3817	1			T8	70		T11	378		T14	606
valid_sources[0x02]	4246	1			T8	71		T11	414		T14	699
valid_sources[0x03]	4977	1			T8	96		T11	354		T14	691
valid_sources[0x04]	5094	1			T8	71		T11	304		T14	656
valid_sources[0x05]	4485	1			T8	69		T11	310		T14	595
valid_sources[0x06]	4247	1			T8	83		T11	316		T14	619
valid_sources[0x07]	4000	1			T8	75		T11	289		T14	697
valid_sources[0x08]	4875	1			T8	64		T11	362		T14	699
valid_sources[0x09]	4079	1			T8	72		T11	294		T14	712
valid_sources[0x0a]	5006	1			T8	72		T11	366		T14	670
valid_sources[0x0b]	4627	1			T8	74		T11	331		T14	617
valid_sources[0x0c]	5122	1			T8	65		T11	280		T14	593
valid_sources[0x0d]	3538	1			T8	79		T11	335		T14	662
valid_sources[0x0e]	4357	1			T8	74		T11	366		T14	755
valid_sources[0x0f]	4537	1			T8	88		T11	381		T14	705
valid_sources[0x10]	4480	1			T8	63		T11	325		T14	635
valid_sources[0x11]	4363	1			T8	71		T11	338		T14	687
valid_sources[0x12]	4995	1			T8	72		T11	329		T14	731
valid_sources[0x13]	3950	1			T8	80		T11	403		T14	631
valid_sources[0x14]	4275	1			T8	63		T11	334		T14	694
valid_sources[0x15]	4840	1			T8	69		T11	344		T14	703
valid_sources[0x16]	4513	1			T8	73		T11	366		T14	650
valid_sources[0x17]	4711	1			T7	3		T8	81		T11	350
valid_sources[0x18]	4985	1			T8	92		T11	345		T14	621
valid_sources[0x19]	3916	1			T8	72		T11	320		T14	669
valid_sources[0x1a]	3836	1			T8	64		T11	329		T14	609
valid_sources[0x1b]	4054	1			T8	74		T11	327		T14	668
valid_sources[0x1c]	4155	1			T8	80		T11	330		T14	561
valid_sources[0x1d]	4418	1			T8	70		T11	365		T14	621
valid_sources[0x1e]	4670	1			T8	78		T11	311		T17	2
valid_sources[0x1f]	3706	1			T8	70		T11	337		T14	651
valid_sources[0x20]	5039	1			T8	76		T11	346		T14	723
valid_sources[0x21]	5563	1			T8	78		T11	333		T17	1
valid_sources[0x22]	4743	1			T8	66		T11	368		T14	663
valid_sources[0x23]	3817	1			T8	78		T11	360		T14	693
valid_sources[0x24]	4552	1			T7	2		T8	69		T11	331
valid_sources[0x25]	3616	1			T2	1		T8	63		T11	369
valid_sources[0x26]	5260	1			T8	66		T11	342		T14	592
valid_sources[0x27]	3780	1			T8	69		T11	324		T14	572
valid_sources[0x28]	4035	1			T7	1		T8	94		T11	369
valid_sources[0x29]	4324	1			T8	76		T11	363		T14	681
valid_sources[0x2a]	4453	1			T8	89		T11	286		T14	637
valid_sources[0x2b]	3943	1			T8	78		T11	311		T14	678
valid_sources[0x2c]	4000	1			T8	80		T11	344		T14	647
valid_sources[0x2d]	4019	1			T8	65		T11	376		T14	614
valid_sources[0x2e]	4604	1			T7	2		T8	61		T11	350
valid_sources[0x2f]	4877	1			T8	69		T11	374		T14	733
valid_sources[0x30]	4795	1			T7	2		T8	72		T11	316
valid_sources[0x31]	5557	1			T7	1		T8	65		T11	286
valid_sources[0x32]	4754	1			T7	1		T8	79		T11	331
valid_sources[0x33]	3228	1			T8	71		T11	383		T14	633
valid_sources[0x34]	3923	1			T8	66		T11	350		T14	695
valid_sources[0x35]	4723	1			T8	77		T11	345		T14	648
valid_sources[0x36]	4284	1			T7	4		T8	69		T11	349
valid_sources[0x37]	5064	1			T8	86		T11	353		T14	647
valid_sources[0x38]	4097	1			T8	64		T11	338		T14	663
valid_sources[0x39]	3715	1			T8	76		T11	315		T14	601
valid_sources[0x3a]	3855	1			T8	73		T11	353		T14	605
valid_sources[0x3b]	4792	1			T8	68		T11	331		T14	684
valid_sources[0x3c]	3860	1			T8	72		T11	346		T14	646
valid_sources[0x3d]	4523	1			T8	88		T11	336		T14	755
valid_sources[0x3e]	4845	1			T8	64		T11	404		T14	661
valid_sources[0x3f]	4365	1			T8	85		T11	339		T14	662
valid_sources[0x40]	4086	1			T8	73		T11	341		T14	653
valid_sources[0x41]	3452	1			T7	1		T8	75		T11	426
valid_sources[0x42]	4812	1			T8	65		T11	344		T14	660
valid_sources[0x43]	3702	1			T3	1		T8	72		T11	384
valid_sources[0x44]	3906	1			T8	91		T11	354		T17	1
valid_sources[0x45]	4488	1			T8	73		T11	380		T14	732
valid_sources[0x46]	4315	1			T8	70		T11	335		T17	2
valid_sources[0x47]	3721	1			T8	72		T11	366		T14	644
valid_sources[0x48]	4441	1			T7	1		T8	73		T11	329
valid_sources[0x49]	4273	1			T8	70		T11	356		T22	6
valid_sources[0x4a]	4214	1			T8	67		T11	344		T14	633
valid_sources[0x4b]	4996	1			T8	69		T11	329		T14	720
valid_sources[0x4c]	5123	1			T8	75		T11	409		T14	730
valid_sources[0x4d]	4348	1			T8	87		T11	329		T22	1
valid_sources[0x4e]	4602	1			T8	64		T11	330		T14	706
valid_sources[0x4f]	5151	1			T8	76		T11	321		T14	684
valid_sources[0x50]	3483	1			T8	73		T11	290		T14	606
valid_sources[0x51]	5295	1			T7	5		T8	75		T11	354
valid_sources[0x52]	4274	1			T8	66		T11	416		T14	733
valid_sources[0x53]	4228	1			T8	64		T11	346		T14	659
valid_sources[0x54]	4150	1			T2	1		T8	56		T11	307
valid_sources[0x55]	4113	1			T8	63		T11	355		T14	662
valid_sources[0x56]	3732	1			T8	73		T11	316		T14	651
valid_sources[0x57]	3853	1			T8	77		T11	367		T14	648
valid_sources[0x58]	4525	1			T7	1		T8	63		T11	341
valid_sources[0x59]	3820	1			T8	76		T11	368		T14	717
valid_sources[0x5a]	4431	1			T7	1		T8	84		T11	344
valid_sources[0x5b]	4495	1			T8	86		T11	312		T14	624
valid_sources[0x5c]	4988	1			T8	70		T11	368		T14	669
valid_sources[0x5d]	5259	1			T8	89		T9	1		T11	325
valid_sources[0x5e]	4625	1			T8	72		T11	355		T14	590
valid_sources[0x5f]	4945	1			T8	72		T11	358		T14	648
valid_sources[0x60]	4035	1			T7	2		T8	75		T11	343
valid_sources[0x61]	4820	1			T8	72		T11	368		T14	696
valid_sources[0x62]	4225	1			T8	65		T11	296		T14	636
valid_sources[0x63]	5351	1			T8	76		T11	374		T14	649
valid_sources[0x64]	4313	1			T8	71		T11	347		T14	591
valid_sources[0x65]	4505	1			T8	63		T11	316		T14	665
valid_sources[0x66]	3998	1			T8	78		T11	346		T14	633
valid_sources[0x67]	4886	1			T8	69		T11	332		T14	694
valid_sources[0x68]	5324	1			T8	79		T11	324		T14	622
valid_sources[0x69]	4221	1			T7	3		T8	63		T11	353
valid_sources[0x6a]	4013	1			T7	3		T8	75		T11	391
valid_sources[0x6b]	3811	1			T8	89		T11	357		T14	657
valid_sources[0x6c]	5763	1			T7	5		T8	73		T11	373
valid_sources[0x6d]	4214	1			T7	2		T8	91		T11	427
valid_sources[0x6e]	4043	1			T8	78		T11	376		T14	646
valid_sources[0x6f]	4762	1			T8	65		T11	356		T14	688
valid_sources[0x70]	3782	1			T8	71		T11	389		T14	569
valid_sources[0x71]	4198	1			T8	72		T11	346		T14	636
valid_sources[0x72]	4030	1			T8	69		T11	333		T14	745
valid_sources[0x73]	5178	1			T2	1		T8	69		T11	338
valid_sources[0x74]	4279	1			T8	77		T11	380		T14	647
valid_sources[0x75]	5026	1			T2	1		T8	65		T11	374
valid_sources[0x76]	4325	1			T8	74		T11	374		T14	646
valid_sources[0x77]	4553	1			T8	49		T11	336		T14	694
valid_sources[0x78]	4467	1			T2	1		T8	72		T11	344
valid_sources[0x79]	3875	1			T8	64		T11	344		T14	623
valid_sources[0x7a]	3299	1			T8	75		T11	331		T14	575
valid_sources[0x7b]	4437	1			T8	72		T11	326		T14	687
valid_sources[0x7c]	4307	1			T8	67		T11	335		T14	734
valid_sources[0x7d]	5147	1			T8	68		T11	361		T14	730
valid_sources[0x7e]	4210	1			T8	73		T11	256		T14	638
valid_sources[0x7f]	5104	1			T8	61		T11	347		T17	1
valid_sources[0x80]	4296	1			T8	60		T11	381		T14	616

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

257477

1

T1

1

T3

1

T5

1

values[0x0]

all_enables

biggest_size

384922

1

T2

1

T8

6363

T11

30539

values[0x1]

all_enables

biggest_size

385166

1

T8

6321

T11

30268

T16

1