Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2451873

1

T4

191

T6

107

T7

127

full_word

1570536

1

T4

13

T6

6

T7

19

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4022099	1			T4	204		T6	113		T7	146
auto[TlIntgErrCmd]	88	1			T55	5		T56	5		T57	7
auto[TlIntgErrData]	112	1			T55	9		T56	7		T57	6
auto[TlIntgErrBoth]	110	1			T55	6		T56	8		T57	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

630396

1

T4

204

T6

113

T7

146

auto[1]

3392013

1

T8

52941

T11

260430

T14

519197

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	260518	1			T4	191		T6	107		T7	127
auto[TlIntgErrNone]	partial	auto[1]	2191075	1			T8	34190		T11	166929		T14	333801
auto[TlIntgErrNone]	full_word	auto[0]	369739	1			T4	13		T6	6		T7	19
auto[TlIntgErrNone]	full_word	auto[1]	1200767	1			T8	18751		T11	93501		T14	185396
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T55	3		T56	3		T57	3
auto[TlIntgErrCmd]	partial	auto[1]	40	1			T55	2		T56	1		T57	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T115	1		T116	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T56	1		T57	1		T112	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T55	5		T56	4		T57	1
auto[TlIntgErrData]	partial	auto[1]	51	1			T55	3		T56	2		T57	5
auto[TlIntgErrData]	full_word	auto[0]	5	1			T56	1		T112	1		T110	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T55	1		T110	1		T114	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T55	3		T56	3		T57	2
auto[TlIntgErrBoth]	partial	auto[1]	61	1			T55	3		T56	4		T57	5
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T56	1		T117	1		T118	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T112	1		T115	1		T119	1