SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.rom_ctrl_regs_csr_assert | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
93.05 | 100.00 | 98.28 | 97.26 | 100.00 | 69.70 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
TlulOOBAddrErr_A | 85406324 | 1835805 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 85406324 | 1835805 | 0 | 0 |
T8 | 939895 | 29589 | 0 | 0 |
T9 | 196741 | 0 | 0 | 0 |
T10 | 51788 | 0 | 0 | 0 |
T11 | 468516 | 151932 | 0 | 0 |
T13 | 17430 | 0 | 0 | 0 |
T14 | 597976 | 274739 | 0 | 0 |
T16 | 24737 | 0 | 0 | 0 |
T17 | 240390 | 0 | 0 | 0 |
T18 | 273723 | 0 | 0 | 0 |
T22 | 24720 | 0 | 0 | 0 |
T43 | 0 | 42354 | 0 | 0 |
T46 | 0 | 279699 | 0 | 0 |
T50 | 0 | 32260 | 0 | 0 |
T51 | 0 | 279120 | 0 | 0 |
T52 | 0 | 235679 | 0 | 0 |
T53 | 0 | 52390 | 0 | 0 |
T54 | 0 | 71856 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |