Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2866699

1

T3

170517

T4

45

T6

350

full_word

1825769

1

T1

2

T3

109022

T4

8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4692208	1			T1	2		T3	279539		T4	53
auto[TlIntgErrCmd]	92	1			T52	1		T53	6		T54	3
auto[TlIntgErrData]	87	1			T52	5		T53	4		T54	4
auto[TlIntgErrBoth]	81	1			T52	4		T54	3		T96	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

733353

1

T1

2

T3

41899

T4

53

auto[1]

3959115

1

T3

237640

T15

152050

T12

77940

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	303098	1			T3	16421		T4	45		T6	350
auto[TlIntgErrNone]	partial	auto[1]	2563364	1			T3	154096		T15	99928		T12	48977
auto[TlIntgErrNone]	full_word	auto[0]	430139	1			T1	2		T3	25478		T4	8
auto[TlIntgErrNone]	full_word	auto[1]	1395607	1			T3	83544		T15	52122		T12	28963
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T53	2		T54	2		T96	2
auto[TlIntgErrCmd]	partial	auto[1]	47	1			T52	1		T53	3		T54	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T93	3		T99	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T53	1		T91	1		T100	1
auto[TlIntgErrData]	partial	auto[0]	37	1			T52	2		T53	2		T54	2
auto[TlIntgErrData]	partial	auto[1]	43	1			T52	3		T53	2		T54	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T96	1		T99	1		T101	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T102	1		T103	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T52	1		T54	1		T96	2
auto[TlIntgErrBoth]	partial	auto[1]	41	1			T52	3		T54	2		T91	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T96	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T93	1		T98	1		T102	2