Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	58167	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1818983

1

T1

9

T4

10

T7

117915

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	476868	1			T1	9		T4	87		T7	29829
values[0x0]	687264	1			T7	44489		T11	68344		T12	36147
values[0x1]	713018	1			T7	46823		T11	70247		T12	37855

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	31514	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1845636

1

T1

9

T4

49

T7

119265

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6456	1			T7	482		T19	1		T89	1
valid_sources[0x01]	9728	1			T7	481		T11	763		T108	20
valid_sources[0x02]	7820	1			T7	443		T19	2		T89	1
valid_sources[0x03]	7361	1			T7	467		T19	1		T89	3
valid_sources[0x04]	5992	1			T7	482		T19	2		T11	729
valid_sources[0x05]	6458	1			T7	488		T8	3		T89	3
valid_sources[0x06]	6895	1			T7	483		T19	2		T62	26
valid_sources[0x07]	7359	1			T7	471		T16	1		T89	1
valid_sources[0x08]	6807	1			T7	471		T11	718		T91	1
valid_sources[0x09]	7810	1			T7	462		T89	1		T11	706
valid_sources[0x0a]	7875	1			T7	485		T89	3		T11	716
valid_sources[0x0b]	7196	1			T7	462		T19	1		T89	1
valid_sources[0x0c]	6266	1			T7	506		T19	1		T11	770
valid_sources[0x0d]	5783	1			T7	496		T8	1		T89	3
valid_sources[0x0e]	7316	1			T7	502		T89	1		T11	704
valid_sources[0x0f]	6868	1			T7	464		T19	3		T89	1
valid_sources[0x10]	8601	1			T7	495		T89	1		T11	700
valid_sources[0x11]	6368	1			T7	444		T19	1		T11	679
valid_sources[0x12]	8431	1			T7	469		T89	2		T11	713
valid_sources[0x13]	7539	1			T7	439		T89	1		T11	730
valid_sources[0x14]	6549	1			T7	481		T19	3		T11	770
valid_sources[0x15]	7401	1			T7	439		T11	708		T32	1
valid_sources[0x16]	6521	1			T7	497		T8	1		T19	1
valid_sources[0x17]	7399	1			T7	508		T89	1		T11	747
valid_sources[0x18]	6311	1			T7	453		T19	2		T89	1
valid_sources[0x19]	5601	1			T7	503		T19	2		T11	675
valid_sources[0x1a]	6127	1			T7	468		T8	1		T19	2
valid_sources[0x1b]	8259	1			T7	445		T11	738		T32	1
valid_sources[0x1c]	7208	1			T1	2		T7	450		T19	1
valid_sources[0x1d]	5440	1			T7	489		T89	1		T11	737
valid_sources[0x1e]	7231	1			T7	462		T11	741		T32	4
valid_sources[0x1f]	8216	1			T7	468		T11	675		T90	3
valid_sources[0x20]	7193	1			T7	474		T89	1		T11	736
valid_sources[0x21]	8150	1			T7	459		T19	1		T11	684
valid_sources[0x22]	6759	1			T7	454		T10	34		T89	2
valid_sources[0x23]	7517	1			T7	458		T19	1		T89	1
valid_sources[0x24]	8634	1			T7	482		T19	1		T89	2
valid_sources[0x25]	8403	1			T7	481		T11	748		T32	1
valid_sources[0x26]	8670	1			T7	468		T19	1		T11	729
valid_sources[0x27]	7753	1			T7	487		T8	1		T19	8
valid_sources[0x28]	7416	1			T7	489		T89	1		T11	734
valid_sources[0x29]	8874	1			T7	512		T11	774		T29	6
valid_sources[0x2a]	5685	1			T7	456		T11	751		T32	1
valid_sources[0x2b]	7262	1			T7	468		T18	1		T19	1
valid_sources[0x2c]	7929	1			T7	485		T19	3		T11	752
valid_sources[0x2d]	6362	1			T7	470		T19	7		T16	1
valid_sources[0x2e]	7656	1			T7	501		T89	2		T11	742
valid_sources[0x2f]	7137	1			T7	461		T19	2		T11	756
valid_sources[0x30]	5917	1			T7	478		T19	3		T89	1
valid_sources[0x31]	7957	1			T7	423		T11	706		T91	2
valid_sources[0x32]	7242	1			T7	471		T19	3		T11	719
valid_sources[0x33]	8503	1			T7	479		T19	3		T11	709
valid_sources[0x34]	6605	1			T7	458		T17	1		T89	2
valid_sources[0x35]	8785	1			T7	444		T19	3		T11	721
valid_sources[0x36]	7965	1			T7	482		T89	1		T11	669
valid_sources[0x37]	6253	1			T7	467		T19	4		T11	702
valid_sources[0x38]	8948	1			T4	20		T7	452		T19	4
valid_sources[0x39]	7015	1			T7	463		T19	2		T11	823
valid_sources[0x3a]	7393	1			T7	446		T89	1		T11	707
valid_sources[0x3b]	7739	1			T7	495		T89	1		T11	730
valid_sources[0x3c]	6504	1			T7	482		T19	1		T16	1
valid_sources[0x3d]	8168	1			T7	477		T89	1		T11	737
valid_sources[0x3e]	7189	1			T7	478		T19	1		T89	2
valid_sources[0x3f]	5622	1			T7	497		T19	3		T62	47
valid_sources[0x40]	7623	1			T7	497		T89	1		T11	687
valid_sources[0x41]	6200	1			T7	489		T8	1		T11	716
valid_sources[0x42]	7289	1			T1	1		T7	465		T8	1
valid_sources[0x43]	8062	1			T7	470		T19	1		T16	1
valid_sources[0x44]	8644	1			T7	502		T20	1		T89	2
valid_sources[0x45]	6451	1			T7	453		T89	2		T11	721
valid_sources[0x46]	7101	1			T7	507		T11	744		T92	1
valid_sources[0x47]	9594	1			T7	432		T19	1		T11	720
valid_sources[0x48]	9079	1			T7	515		T19	1		T89	1
valid_sources[0x49]	6521	1			T7	444		T19	4		T89	2
valid_sources[0x4a]	5005	1			T7	509		T89	1		T11	735
valid_sources[0x4b]	5778	1			T7	476		T19	1		T11	707
valid_sources[0x4c]	6667	1			T7	483		T19	1		T89	1
valid_sources[0x4d]	7510	1			T7	487		T89	1		T11	698
valid_sources[0x4e]	5767	1			T7	525		T19	1		T89	1
valid_sources[0x4f]	6466	1			T7	469		T19	5		T89	3
valid_sources[0x50]	6972	1			T7	427		T17	2		T11	702
valid_sources[0x51]	6152	1			T7	468		T10	35		T11	747
valid_sources[0x52]	8138	1			T7	462		T8	1		T19	2
valid_sources[0x53]	7082	1			T7	454		T16	1		T89	5
valid_sources[0x54]	8113	1			T7	476		T19	2		T89	1
valid_sources[0x55]	7439	1			T7	457		T19	3		T89	2
valid_sources[0x56]	5792	1			T7	459		T89	1		T11	723
valid_sources[0x57]	5611	1			T7	492		T89	1		T11	688
valid_sources[0x58]	7969	1			T7	523		T8	1		T19	3
valid_sources[0x59]	7885	1			T7	484		T8	1		T19	2
valid_sources[0x5a]	6274	1			T7	453		T11	692		T32	3
valid_sources[0x5b]	6468	1			T7	479		T19	1		T89	1
valid_sources[0x5c]	6257	1			T7	466		T8	2		T89	1
valid_sources[0x5d]	5765	1			T7	505		T19	1		T11	716
valid_sources[0x5e]	5960	1			T7	464		T8	1		T19	1
valid_sources[0x5f]	6293	1			T7	451		T89	1		T11	720
valid_sources[0x60]	6794	1			T7	480		T89	1		T11	673
valid_sources[0x61]	9125	1			T7	477		T11	717		T32	1
valid_sources[0x62]	8295	1			T4	44		T7	490		T19	4
valid_sources[0x63]	6848	1			T7	454		T89	3		T11	719
valid_sources[0x64]	9850	1			T7	475		T17	3		T89	1
valid_sources[0x65]	6374	1			T7	493		T89	1		T11	710
valid_sources[0x66]	9470	1			T1	2		T7	487		T11	740
valid_sources[0x67]	6964	1			T7	463		T17	1		T11	725
valid_sources[0x68]	6949	1			T7	522		T10	17		T19	1
valid_sources[0x69]	7767	1			T7	482		T19	1		T89	1
valid_sources[0x6a]	7629	1			T7	467		T8	1		T10	19
valid_sources[0x6b]	6507	1			T7	503		T17	1		T11	747
valid_sources[0x6c]	7566	1			T7	481		T11	671		T91	2
valid_sources[0x6d]	7841	1			T7	501		T19	3		T11	730
valid_sources[0x6e]	8391	1			T7	477		T19	1		T89	1
valid_sources[0x6f]	7587	1			T7	506		T89	1		T11	685
valid_sources[0x70]	7969	1			T7	484		T19	4		T11	765
valid_sources[0x71]	8039	1			T7	467		T19	1		T11	735
valid_sources[0x72]	10476	1			T7	495		T19	1		T89	3
valid_sources[0x73]	7960	1			T7	443		T8	1		T11	730
valid_sources[0x74]	10521	1			T7	426		T89	1		T11	696
valid_sources[0x75]	7383	1			T7	482		T10	10		T11	691
valid_sources[0x76]	7926	1			T7	436		T19	2		T89	3
valid_sources[0x77]	5814	1			T7	464		T89	1		T11	722
valid_sources[0x78]	7081	1			T7	501		T11	706		T32	1
valid_sources[0x79]	7515	1			T7	489		T11	716		T92	1
valid_sources[0x7a]	8019	1			T7	442		T11	703		T32	2
valid_sources[0x7b]	8129	1			T7	499		T11	745		T32	1
valid_sources[0x7c]	5466	1			T7	463		T8	1		T62	12
valid_sources[0x7d]	7595	1			T7	464		T11	741		T32	2
valid_sources[0x7e]	7323	1			T7	482		T19	4		T11	721
valid_sources[0x7f]	5845	1			T7	491		T19	6		T11	702
valid_sources[0x80]	5443	1			T7	457		T19	2		T11	732

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

455721

1

T1

9

T4

10

T7

29235

values[0x0]

all_enables

biggest_size

681313

1

T7

44023

T11

67811

T12

35907

values[0x1]

all_enables

biggest_size

681949

1

T7

44657

T11

67259

T12

36263

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	131303	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1373934

1

T1

10

T2

2

T3

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	369692	1			T1	28		T4	32		T6	22
values[0x0]	526280	1			T2	2		T3	2		T5	4
values[0x1]	609265	1			T2	3		T3	8		T5	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	57265	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1447972

1

T1

15

T2

2

T3

5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5549	1			T7	635		T15	3		T17	1
valid_sources[0x01]	5972	1			T7	201		T11	192		T109	2
valid_sources[0x02]	5199	1			T7	374		T11	464		T31	1
valid_sources[0x03]	5647	1			T7	148		T11	857		T30	1
valid_sources[0x04]	4798	1			T7	208		T11	2		T12	311
valid_sources[0x05]	5763	1			T7	653		T11	508		T12	310
valid_sources[0x06]	6276	1			T7	692		T15	1		T11	620
valid_sources[0x07]	5349	1			T7	576		T11	214		T39	29
valid_sources[0x08]	6747	1			T7	226		T15	8		T17	1
valid_sources[0x09]	5033	1			T7	267		T17	1		T61	1
valid_sources[0x0a]	6494	1			T7	545		T9	1		T11	270
valid_sources[0x0b]	6888	1			T7	548		T11	703		T109	3
valid_sources[0x0c]	5382	1			T7	33		T11	501		T30	2
valid_sources[0x0d]	5312	1			T7	688		T61	1		T11	463
valid_sources[0x0e]	5891	1			T7	223		T9	2		T11	394
valid_sources[0x0f]	6349	1			T7	547		T20	1		T11	634
valid_sources[0x10]	7099	1			T7	995		T11	704		T110	1
valid_sources[0x11]	5966	1			T7	378		T11	867		T12	322
valid_sources[0x12]	6521	1			T7	386		T11	613		T110	1
valid_sources[0x13]	6831	1			T7	155		T11	867		T12	295
valid_sources[0x14]	5379	1			T7	56		T11	562		T38	3
valid_sources[0x15]	5835	1			T7	482		T11	720		T110	1
valid_sources[0x16]	6382	1			T7	612		T11	724		T110	1
valid_sources[0x17]	5740	1			T6	6		T7	195		T17	2
valid_sources[0x18]	5432	1			T7	289		T11	236		T72	1
valid_sources[0x19]	5324	1			T7	170		T11	343		T12	255
valid_sources[0x1a]	6655	1			T7	396		T11	1181		T110	1
valid_sources[0x1b]	6867	1			T7	273		T11	963		T12	296
valid_sources[0x1c]	5079	1			T7	297		T11	234		T12	307
valid_sources[0x1d]	5945	1			T7	293		T11	686		T38	1
valid_sources[0x1e]	5172	1			T7	331		T11	305		T72	2
valid_sources[0x1f]	4987	1			T7	373		T11	5		T12	303
valid_sources[0x20]	5426	1			T7	576		T11	543		T12	322
valid_sources[0x21]	6201	1			T7	905		T111	1		T11	458
valid_sources[0x22]	7480	1			T7	445		T11	1806		T30	1
valid_sources[0x23]	5549	1			T7	330		T11	718		T12	271
valid_sources[0x24]	5352	1			T7	306		T17	2		T20	2
valid_sources[0x25]	6330	1			T7	607		T11	213		T12	292
valid_sources[0x26]	5508	1			T7	452		T11	369		T112	1
valid_sources[0x27]	6219	1			T7	337		T11	448		T38	2
valid_sources[0x28]	5424	1			T7	321		T11	302		T12	296
valid_sources[0x29]	6276	1			T7	496		T20	1		T11	685
valid_sources[0x2a]	5718	1			T5	1		T7	618		T17	1
valid_sources[0x2b]	6139	1			T7	632		T11	195		T113	1
valid_sources[0x2c]	5951	1			T7	408		T11	374		T12	266
valid_sources[0x2d]	6698	1			T7	507		T11	1254		T12	308
valid_sources[0x2e]	6285	1			T6	3		T7	473		T11	649
valid_sources[0x2f]	6205	1			T7	285		T11	1073		T110	1
valid_sources[0x30]	5100	1			T6	9		T7	239		T11	502
valid_sources[0x31]	5480	1			T7	457		T15	1		T11	224
valid_sources[0x32]	6144	1			T7	718		T11	775		T72	1
valid_sources[0x33]	6240	1			T7	784		T20	1		T11	549
valid_sources[0x34]	5456	1			T7	312		T11	321		T72	1
valid_sources[0x35]	5391	1			T7	49		T9	1		T11	484
valid_sources[0x36]	6902	1			T7	1058		T11	884		T93	2
valid_sources[0x37]	5624	1			T7	112		T20	1		T11	849
valid_sources[0x38]	5672	1			T7	357		T11	229		T30	1
valid_sources[0x39]	6107	1			T6	4		T7	247		T20	1
valid_sources[0x3a]	5374	1			T7	134		T17	1		T11	794
valid_sources[0x3b]	5919	1			T7	457		T11	773		T30	1
valid_sources[0x3c]	5837	1			T2	1		T7	183		T17	1
valid_sources[0x3d]	6384	1			T7	381		T11	373		T33	1
valid_sources[0x3e]	5574	1			T7	391		T17	1		T11	97
valid_sources[0x3f]	6003	1			T7	813		T11	552		T12	290
valid_sources[0x40]	6383	1			T7	571		T11	730		T109	2
valid_sources[0x41]	5510	1			T7	412		T11	423		T114	1
valid_sources[0x42]	7301	1			T7	397		T17	1		T11	879
valid_sources[0x43]	5395	1			T5	2		T7	116		T20	1
valid_sources[0x44]	6764	1			T7	402		T61	1		T11	843
valid_sources[0x45]	5870	1			T7	158		T9	1		T11	521
valid_sources[0x46]	7885	1			T7	699		T11	1021		T12	287
valid_sources[0x47]	5924	1			T7	240		T11	1038		T12	312
valid_sources[0x48]	5456	1			T7	60		T11	555		T12	277
valid_sources[0x49]	6038	1			T7	313		T11	451		T30	2
valid_sources[0x4a]	5842	1			T7	430		T9	1		T11	644
valid_sources[0x4b]	5750	1			T3	3		T7	312		T20	1
valid_sources[0x4c]	5565	1			T7	393		T11	285		T33	1
valid_sources[0x4d]	5752	1			T7	366		T11	308		T38	1
valid_sources[0x4e]	5465	1			T7	165		T11	648		T12	296
valid_sources[0x4f]	5807	1			T7	455		T20	1		T11	127
valid_sources[0x50]	4931	1			T7	480		T11	363		T12	322
valid_sources[0x51]	6613	1			T7	589		T11	799		T72	1
valid_sources[0x52]	5045	1			T7	591		T11	453		T12	324
valid_sources[0x53]	5373	1			T7	241		T11	479		T38	3
valid_sources[0x54]	6504	1			T7	722		T11	840		T38	1
valid_sources[0x55]	5506	1			T7	382		T20	1		T11	640
valid_sources[0x56]	6065	1			T7	146		T20	1		T11	389
valid_sources[0x57]	5992	1			T7	331		T20	1		T11	505
valid_sources[0x58]	5512	1			T7	238		T11	713		T12	324
valid_sources[0x59]	5119	1			T7	540		T11	365		T30	1
valid_sources[0x5a]	5597	1			T7	249		T11	586		T12	279
valid_sources[0x5b]	5078	1			T7	118		T11	4		T12	283
valid_sources[0x5c]	5595	1			T7	416		T11	546		T12	297
valid_sources[0x5d]	5759	1			T5	2		T7	178		T11	949
valid_sources[0x5e]	6248	1			T7	426		T11	537		T93	1
valid_sources[0x5f]	5499	1			T7	595		T11	7		T12	313
valid_sources[0x60]	5303	1			T7	279		T11	456		T12	308
valid_sources[0x61]	5908	1			T7	467		T20	1		T11	466
valid_sources[0x62]	6638	1			T7	619		T11	307		T92	16
valid_sources[0x63]	4741	1			T7	200		T8	16		T11	106
valid_sources[0x64]	6280	1			T7	577		T11	481		T115	16
valid_sources[0x65]	5352	1			T7	148		T11	312		T114	1
valid_sources[0x66]	5877	1			T7	334		T11	722		T72	1
valid_sources[0x67]	4991	1			T7	381		T11	230		T116	2
valid_sources[0x68]	6859	1			T7	397		T11	976		T12	325
valid_sources[0x69]	5808	1			T7	165		T11	455		T12	313
valid_sources[0x6a]	5059	1			T7	257		T11	355		T12	299
valid_sources[0x6b]	5035	1			T7	466		T11	36		T12	321
valid_sources[0x6c]	5909	1			T7	368		T24	1		T20	1
valid_sources[0x6d]	6323	1			T7	501		T11	1150		T38	2
valid_sources[0x6e]	5600	1			T7	316		T17	1		T11	712
valid_sources[0x6f]	5607	1			T7	611		T11	279		T12	278
valid_sources[0x70]	5266	1			T7	516		T11	135		T110	1
valid_sources[0x71]	5124	1			T7	56		T11	324		T30	1
valid_sources[0x72]	7331	1			T7	1087		T61	1		T11	882
valid_sources[0x73]	5575	1			T7	48		T11	698		T30	1
valid_sources[0x74]	5803	1			T7	529		T11	635		T72	1
valid_sources[0x75]	5739	1			T7	445		T11	294		T35	1
valid_sources[0x76]	5686	1			T7	36		T11	469		T114	1
valid_sources[0x77]	5334	1			T7	175		T11	731		T12	299
valid_sources[0x78]	6038	1			T7	537		T18	4		T20	2
valid_sources[0x79]	5378	1			T7	352		T11	153		T38	7
valid_sources[0x7a]	6471	1			T7	550		T11	890		T12	308
valid_sources[0x7b]	6042	1			T7	444		T11	840		T114	1
valid_sources[0x7c]	5463	1			T7	580		T11	263		T30	1
valid_sources[0x7d]	5861	1			T7	282		T11	695		T93	3
valid_sources[0x7e]	5324	1			T7	252		T11	564		T30	1
valid_sources[0x7f]	5623	1			T7	339		T11	554		T12	327
valid_sources[0x80]	5434	1			T7	362		T17	2		T20	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

344048

1

T1

10

T4

17

T6

11

values[0x0]

all_enables

biggest_size

515617

1

T7

34852

T9

1

T61

3

values[0x1]

all_enables

biggest_size

514269

1

T2

2

T3

2

T7

34921