Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3292846

1

T4

77

T7

227668

T8

44

full_word

2121891

1

T1

6

T4

10

T7

139112

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	5414437	1			T1	6		T4	87		T7	366780
auto[TlIntgErrCmd]	97	1			T56	6		T57	3		T58	4
auto[TlIntgErrData]	96	1			T56	7		T57	1		T58	2
auto[TlIntgErrBoth]	107	1			T56	7		T57	6		T58	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

844310

1

T1

6

T4

87

T7

55217

auto[1]

4570427

1

T7

311563

T11

448108

T12

236565

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	344803	1			T4	77		T7	22926		T8	44
auto[TlIntgErrNone]	partial	auto[1]	2947772	1			T7	204742		T11	287771		T12	151221
auto[TlIntgErrNone]	full_word	auto[0]	499373	1			T1	6		T4	10		T7	32291
auto[TlIntgErrNone]	full_word	auto[1]	1622489	1			T7	106821		T11	160337		T12	85344
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T56	3		T57	3		T58	1
auto[TlIntgErrCmd]	partial	auto[1]	49	1			T56	2		T58	3		T97	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T98	1		T102	1		T103	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T56	1		T98	1		T103	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T56	3		T57	1		T104	3
auto[TlIntgErrData]	partial	auto[1]	37	1			T56	3		T58	2		T97	5
auto[TlIntgErrData]	full_word	auto[0]	7	1			T56	1		T104	1		T99	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T98	1		T105	1		T106	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T56	2		T57	2		T58	1
auto[TlIntgErrBoth]	partial	auto[1]	63	1			T56	3		T57	4		T58	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T56	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T56	1		T97	1		T100	1