Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2001536

1

T3

57

T4

139

T7

24

full_word

1286727

1

T1

4

T2

2

T3

7

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3287953	1			T1	4		T2	2		T3	64
auto[TlIntgErrCmd]	100	1			T62	4		T63	1		T64	4
auto[TlIntgErrData]	98	1			T62	7		T63	2		T64	2
auto[TlIntgErrBoth]	112	1			T62	9		T63	7		T64	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

520211

1

T1

4

T2

2

T3

64

auto[1]

2768052

1

T14

193298

T15

109084

T16

425728

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	215554	1			T3	57		T4	139		T7	24
auto[TlIntgErrNone]	partial	auto[1]	1785690	1			T14	126536		T15	72661		T16	276608
auto[TlIntgErrNone]	full_word	auto[0]	304522	1			T1	4		T2	2		T3	7
auto[TlIntgErrNone]	full_word	auto[1]	982187	1			T14	66762		T15	36423		T16	149120
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T62	2		T63	1		T64	2
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T62	2		T64	2		T108	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T118	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T108	1		T110	1		T119	1
auto[TlIntgErrData]	partial	auto[0]	38	1			T62	4		T63	1		T108	7
auto[TlIntgErrData]	partial	auto[1]	54	1			T62	3		T63	1		T64	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T64	1		T120	1		T115	1
auto[TlIntgErrData]	full_word	auto[1]	1	1			T109	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	49	1			T62	6		T63	3		T64	1
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T62	2		T63	4		T64	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T108	1		T115	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T62	1		T64	1		T109	1