Unified Coverage Report :: Module :: rom_ctrl_regs_csr_assert_fpv

Module : rom_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rom_ctrl_csr_assert_0/rom_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rom_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rom_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.05	100.00	98.28	97.26		100.00	69.70	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rom_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	69549313	1477521	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69549313	1477521	0	0
T14	233621	102920	0	0
T15	130615	56618	0	0
T16	0	226211	0	0
T17	0	25934	0	0
T47	49440	0	0	0
T49	0	66931	0	0
T50	0	84361	0	0
T51	0	350692	0	0
T52	0	40670	0	0
T53	0	127168	0	0
T54	0	63236	0	0
T55	16617	0	0	0
T56	53972	0	0	0
T57	17387	0	0	0
T58	49697	0	0	0
T59	17587	0	0	0
T60	16739	0	0	0
T61	17401	0	0	0