Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	52285	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1602737

1

T1

3

T3

12

T4

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	420554	1			T1	3		T3	122		T4	3
values[0x0]	606458	1			T12	94605		T13	103017		T15	14080
values[0x1]	628010	1			T12	97751		T13	106901		T15	14695

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28008	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1627014

1

T1

3

T3

76

T4

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5923	1			T5	2		T12	971		T19	1
valid_sources[0x01]	7589	1			T12	1006		T13	2158		T118	3
valid_sources[0x02]	6341	1			T12	1008		T13	551		T15	258
valid_sources[0x03]	7167	1			T11	1		T12	1012		T13	957
valid_sources[0x04]	6135	1			T5	3		T11	5		T12	1004
valid_sources[0x05]	6056	1			T5	4		T11	2		T12	1035
valid_sources[0x06]	5723	1			T12	991		T19	5		T13	545
valid_sources[0x07]	5187	1			T11	3		T12	962		T13	381
valid_sources[0x08]	6337	1			T12	977		T19	6		T13	1452
valid_sources[0x09]	5577	1			T12	1013		T55	2		T13	155
valid_sources[0x0a]	7732	1			T12	1014		T19	1		T55	1
valid_sources[0x0b]	5436	1			T5	1		T12	970		T16	1
valid_sources[0x0c]	5221	1			T5	3		T12	1004		T19	1
valid_sources[0x0d]	7808	1			T12	1023		T16	1		T13	1874
valid_sources[0x0e]	7489	1			T11	1		T12	981		T19	5
valid_sources[0x0f]	6731	1			T12	975		T13	1797		T15	89
valid_sources[0x10]	7034	1			T5	2		T12	987		T13	1467
valid_sources[0x11]	6633	1			T11	1		T12	966		T19	14
valid_sources[0x12]	6402	1			T11	2		T12	967		T13	606
valid_sources[0x13]	6166	1			T12	1028		T56	2		T13	904
valid_sources[0x14]	5904	1			T5	1		T12	1055		T56	2
valid_sources[0x15]	8759	1			T5	3		T11	7		T12	990
valid_sources[0x16]	7344	1			T11	1		T12	1008		T13	1699
valid_sources[0x17]	7569	1			T5	1		T11	1		T12	1005
valid_sources[0x18]	5593	1			T5	5		T12	991		T19	1
valid_sources[0x19]	5367	1			T5	1		T12	1017		T13	268
valid_sources[0x1a]	5190	1			T12	976		T13	181		T61	2
valid_sources[0x1b]	6502	1			T12	1058		T19	5		T13	68
valid_sources[0x1c]	5473	1			T12	990		T36	2		T119	1
valid_sources[0x1d]	7387	1			T5	1		T12	1015		T19	8
valid_sources[0x1e]	6151	1			T11	4		T12	965		T13	341
valid_sources[0x1f]	5443	1			T12	972		T19	8		T13	637
valid_sources[0x20]	5372	1			T12	1000		T56	3		T13	518
valid_sources[0x21]	4957	1			T11	6		T12	1006		T19	2
valid_sources[0x22]	7152	1			T5	1		T12	981		T56	2
valid_sources[0x23]	5233	1			T12	1098		T19	1		T13	118
valid_sources[0x24]	6288	1			T5	3		T12	957		T55	1
valid_sources[0x25]	6389	1			T4	3		T11	4		T12	974
valid_sources[0x26]	5602	1			T11	4		T12	964		T13	423
valid_sources[0x27]	6141	1			T5	10		T12	986		T55	3
valid_sources[0x28]	6347	1			T11	3		T12	1021		T19	6
valid_sources[0x29]	5455	1			T1	3		T11	2		T12	988
valid_sources[0x2a]	5958	1			T12	958		T19	4		T55	4
valid_sources[0x2b]	7872	1			T5	2		T12	990		T19	8
valid_sources[0x2c]	6728	1			T5	8		T12	1031		T55	7
valid_sources[0x2d]	6837	1			T12	959		T56	1		T13	1480
valid_sources[0x2e]	6507	1			T11	2		T12	979		T19	1
valid_sources[0x2f]	6604	1			T5	2		T12	988		T16	1
valid_sources[0x30]	6026	1			T11	4		T12	917		T55	2
valid_sources[0x31]	6411	1			T11	4		T12	1008		T19	7
valid_sources[0x32]	6351	1			T6	1		T12	1006		T19	2
valid_sources[0x33]	5933	1			T11	5		T12	1023		T19	2
valid_sources[0x34]	6648	1			T6	1		T11	1		T12	966
valid_sources[0x35]	7225	1			T12	1047		T13	1207		T98	77
valid_sources[0x36]	7530	1			T12	962		T13	2097		T118	1
valid_sources[0x37]	7040	1			T3	16		T5	5		T11	4
valid_sources[0x38]	7130	1			T12	1046		T13	1925		T120	41
valid_sources[0x39]	5446	1			T12	963		T19	7		T13	181
valid_sources[0x3a]	5315	1			T12	1011		T13	127		T121	1
valid_sources[0x3b]	6309	1			T5	4		T12	1013		T19	8
valid_sources[0x3c]	6170	1			T12	1054		T13	935		T118	1
valid_sources[0x3d]	6013	1			T12	1050		T16	1		T13	601
valid_sources[0x3e]	5466	1			T12	943		T13	595		T48	133
valid_sources[0x3f]	6177	1			T5	2		T12	1045		T13	970
valid_sources[0x40]	6586	1			T12	984		T16	1		T13	935
valid_sources[0x41]	5884	1			T11	9		T12	1023		T19	1
valid_sources[0x42]	6203	1			T12	984		T16	1		T13	1237
valid_sources[0x43]	7269	1			T6	1		T11	1		T12	1018
valid_sources[0x44]	6460	1			T12	962		T13	1349		T48	123
valid_sources[0x45]	7276	1			T12	986		T55	2		T13	2353
valid_sources[0x46]	5170	1			T5	5		T11	1		T12	1002
valid_sources[0x47]	6989	1			T6	1		T12	1111		T13	1756
valid_sources[0x48]	7207	1			T11	4		T12	1026		T19	2
valid_sources[0x49]	5224	1			T5	2		T11	1		T12	989
valid_sources[0x4a]	6166	1			T12	1002		T13	797		T122	3
valid_sources[0x4b]	5821	1			T6	1		T12	1056		T19	3
valid_sources[0x4c]	5688	1			T12	1008		T19	1		T16	1
valid_sources[0x4d]	6350	1			T12	1018		T19	1		T56	1
valid_sources[0x4e]	6123	1			T6	1		T11	2		T12	1002
valid_sources[0x4f]	6494	1			T5	2		T12	936		T56	1
valid_sources[0x50]	6008	1			T11	1		T12	946		T19	1
valid_sources[0x51]	5769	1			T12	962		T56	2		T13	911
valid_sources[0x52]	6545	1			T11	4		T12	1054		T19	2
valid_sources[0x53]	7104	1			T5	1		T11	1		T12	977
valid_sources[0x54]	5779	1			T12	995		T19	2		T13	880
valid_sources[0x55]	6508	1			T12	960		T13	984		T100	25
valid_sources[0x56]	5756	1			T5	2		T12	1001		T13	920
valid_sources[0x57]	6117	1			T5	2		T12	1017		T13	581
valid_sources[0x58]	6719	1			T12	1009		T13	1343		T17	3
valid_sources[0x59]	5875	1			T12	1027		T19	5		T13	851
valid_sources[0x5a]	7269	1			T5	6		T6	1		T11	1
valid_sources[0x5b]	5447	1			T12	937		T13	606		T122	1
valid_sources[0x5c]	7354	1			T11	1		T12	915		T55	1
valid_sources[0x5d]	5864	1			T11	4		T12	960		T19	1
valid_sources[0x5e]	5940	1			T5	1		T12	945		T13	658
valid_sources[0x5f]	5445	1			T12	995		T56	1		T13	499
valid_sources[0x60]	5041	1			T12	993		T19	1		T13	281
valid_sources[0x61]	5893	1			T11	4		T12	952		T13	1214
valid_sources[0x62]	7833	1			T5	1		T12	1024		T19	2
valid_sources[0x63]	7097	1			T11	3		T12	967		T13	1049
valid_sources[0x64]	6070	1			T5	2		T11	4		T12	973
valid_sources[0x65]	7850	1			T12	1029		T13	1683		T118	2
valid_sources[0x66]	6750	1			T6	2		T12	1050		T55	1
valid_sources[0x67]	6008	1			T12	994		T13	586		T119	3
valid_sources[0x68]	7513	1			T12	971		T19	6		T56	2
valid_sources[0x69]	6375	1			T11	1		T12	1054		T13	1229
valid_sources[0x6a]	8395	1			T11	1		T12	1033		T55	1
valid_sources[0x6b]	7934	1			T5	1		T12	996		T13	2774
valid_sources[0x6c]	6767	1			T5	3		T11	1		T12	960
valid_sources[0x6d]	6422	1			T5	2		T12	1034		T13	593
valid_sources[0x6e]	5408	1			T12	996		T19	2		T13	262
valid_sources[0x6f]	6632	1			T12	1000		T19	4		T56	1
valid_sources[0x70]	8251	1			T5	5		T12	979		T16	1
valid_sources[0x71]	5440	1			T5	2		T7	2		T12	1025
valid_sources[0x72]	5722	1			T5	2		T6	1		T12	1025
valid_sources[0x73]	6238	1			T3	18		T12	975		T13	402
valid_sources[0x74]	7325	1			T11	3		T12	1004		T13	1485
valid_sources[0x75]	5662	1			T12	1027		T16	2		T13	278
valid_sources[0x76]	6343	1			T12	962		T13	1365		T118	3
valid_sources[0x77]	8077	1			T11	2		T12	952		T19	2
valid_sources[0x78]	5263	1			T12	1002		T19	1		T13	602
valid_sources[0x79]	4794	1			T5	6		T12	951		T13	110
valid_sources[0x7a]	5244	1			T5	1		T12	999		T19	4
valid_sources[0x7b]	6930	1			T5	1		T12	954		T16	1
valid_sources[0x7c]	6613	1			T12	955		T19	2		T13	1257
valid_sources[0x7d]	6899	1			T11	7		T12	994		T13	1586
valid_sources[0x7e]	6895	1			T12	992		T13	1469		T17	1
valid_sources[0x7f]	6070	1			T5	1		T12	1043		T56	1
valid_sources[0x80]	7276	1			T12	975		T13	1784		T99	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

401298

1

T1

3

T3

12

T4

3

values[0x0]

all_enables

biggest_size

601136

1

T12

93810

T13

102084

T15

13963

values[0x1]

all_enables

biggest_size

600303

1

T12

93621

T13

101928

T15

14065

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	116679	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1234974

1

T1

12

T4

13

T6

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	332411	1			T1	27		T4	27		T6	16
values[0x0]	472639	1			T2	4		T10	2		T14	4
values[0x1]	546603	1			T2	2		T10	1		T14	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	51163	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1300490

1

T1

14

T4

17

T6

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4967	1			T6	1		T12	779		T13	880
valid_sources[0x01]	6080	1			T12	751		T13	864		T15	113
valid_sources[0x02]	4971	1			T12	815		T13	874		T61	1
valid_sources[0x03]	4310	1			T12	812		T13	819		T61	1
valid_sources[0x04]	5688	1			T12	838		T13	880		T15	116
valid_sources[0x05]	4801	1			T4	3		T12	734		T13	858
valid_sources[0x06]	4962	1			T12	798		T13	857		T36	1
valid_sources[0x07]	4820	1			T12	795		T13	789		T15	122
valid_sources[0x08]	4927	1			T12	767		T13	893		T15	128
valid_sources[0x09]	5480	1			T12	848		T16	7		T13	870
valid_sources[0x0a]	4693	1			T12	825		T13	870		T36	1
valid_sources[0x0b]	5706	1			T12	719		T13	894		T39	2
valid_sources[0x0c]	6043	1			T12	754		T13	841		T15	116
valid_sources[0x0d]	5190	1			T1	1		T8	1		T12	839
valid_sources[0x0e]	5832	1			T4	2		T12	825		T13	850
valid_sources[0x0f]	5076	1			T12	783		T13	835		T15	120
valid_sources[0x10]	4877	1			T12	733		T13	828		T37	1
valid_sources[0x11]	5727	1			T6	3		T12	804		T13	904
valid_sources[0x12]	5725	1			T12	796		T13	861		T15	123
valid_sources[0x13]	5467	1			T12	832		T13	846		T15	114
valid_sources[0x14]	5245	1			T12	753		T57	4		T13	847
valid_sources[0x15]	5767	1			T12	759		T13	860		T15	133
valid_sources[0x16]	6105	1			T12	789		T13	884		T64	2
valid_sources[0x17]	4588	1			T12	786		T13	834		T36	2
valid_sources[0x18]	5757	1			T12	709		T13	826		T15	91
valid_sources[0x19]	5297	1			T12	797		T13	865		T15	117
valid_sources[0x1a]	4859	1			T12	831		T13	825		T15	137
valid_sources[0x1b]	5269	1			T12	700		T13	892		T15	121
valid_sources[0x1c]	5265	1			T12	773		T47	1		T13	885
valid_sources[0x1d]	5224	1			T12	796		T13	904		T15	146
valid_sources[0x1e]	5234	1			T12	776		T13	852		T15	133
valid_sources[0x1f]	5645	1			T12	863		T13	834		T100	1
valid_sources[0x20]	5683	1			T12	875		T13	871		T37	1
valid_sources[0x21]	5725	1			T12	815		T13	860		T36	2
valid_sources[0x22]	5975	1			T12	711		T13	879		T37	1
valid_sources[0x23]	5260	1			T12	805		T55	1		T13	924
valid_sources[0x24]	6493	1			T12	789		T13	877		T15	111
valid_sources[0x25]	5327	1			T12	859		T13	886		T15	124
valid_sources[0x26]	4642	1			T12	763		T13	879		T15	104
valid_sources[0x27]	5524	1			T12	741		T13	843		T15	119
valid_sources[0x28]	5995	1			T12	787		T13	873		T15	104
valid_sources[0x29]	5275	1			T12	764		T13	869		T36	1
valid_sources[0x2a]	5406	1			T4	1		T12	825		T13	877
valid_sources[0x2b]	5281	1			T12	774		T13	862		T15	121
valid_sources[0x2c]	5763	1			T12	813		T13	857		T15	110
valid_sources[0x2d]	5693	1			T12	848		T13	881		T39	1
valid_sources[0x2e]	5308	1			T12	754		T13	851		T15	103
valid_sources[0x2f]	5895	1			T6	2		T12	792		T13	882
valid_sources[0x30]	4800	1			T12	777		T13	881		T64	1
valid_sources[0x31]	5079	1			T12	837		T13	838		T15	122
valid_sources[0x32]	4874	1			T12	786		T16	4		T13	868
valid_sources[0x33]	5454	1			T12	799		T13	855		T15	103
valid_sources[0x34]	5732	1			T12	834		T13	856		T39	2
valid_sources[0x35]	5353	1			T12	823		T13	864		T36	2
valid_sources[0x36]	5392	1			T4	1		T12	699		T57	8
valid_sources[0x37]	4585	1			T12	762		T13	851		T15	119
valid_sources[0x38]	4762	1			T12	808		T13	923		T15	112
valid_sources[0x39]	4638	1			T4	1		T12	828		T13	879
valid_sources[0x3a]	5746	1			T4	1		T12	772		T13	840
valid_sources[0x3b]	5236	1			T12	743		T13	873		T15	112
valid_sources[0x3c]	5774	1			T12	718		T13	870		T36	1
valid_sources[0x3d]	5386	1			T12	731		T13	888		T15	96
valid_sources[0x3e]	5478	1			T1	1		T12	794		T13	879
valid_sources[0x3f]	5353	1			T12	764		T13	844		T15	120
valid_sources[0x40]	5964	1			T1	1		T12	750		T13	857
valid_sources[0x41]	5718	1			T12	829		T13	891		T37	1
valid_sources[0x42]	5827	1			T12	800		T13	889		T15	124
valid_sources[0x43]	5267	1			T12	809		T13	825		T15	119
valid_sources[0x44]	5627	1			T1	1		T12	759		T13	869
valid_sources[0x45]	5637	1			T12	760		T13	834		T36	1
valid_sources[0x46]	5321	1			T12	841		T13	855		T36	1
valid_sources[0x47]	5659	1			T12	815		T13	857		T39	2
valid_sources[0x48]	5574	1			T4	2		T12	791		T13	895
valid_sources[0x49]	5375	1			T12	815		T13	909		T15	92
valid_sources[0x4a]	5939	1			T1	1		T12	845		T13	872
valid_sources[0x4b]	5174	1			T14	4		T12	766		T13	838
valid_sources[0x4c]	5111	1			T4	4		T12	772		T13	858
valid_sources[0x4d]	5768	1			T12	839		T13	934		T100	1
valid_sources[0x4e]	4518	1			T12	773		T13	848		T15	127
valid_sources[0x4f]	4772	1			T12	802		T13	786		T15	139
valid_sources[0x50]	5092	1			T12	807		T13	875		T15	130
valid_sources[0x51]	5167	1			T12	787		T13	914		T36	1
valid_sources[0x52]	5723	1			T4	1		T12	746		T13	895
valid_sources[0x53]	5507	1			T12	749		T13	917		T15	127
valid_sources[0x54]	5745	1			T12	833		T13	861		T61	1
valid_sources[0x55]	5391	1			T12	841		T13	860		T15	104
valid_sources[0x56]	4886	1			T12	771		T13	834		T15	105
valid_sources[0x57]	4970	1			T1	1		T4	2		T12	789
valid_sources[0x58]	4971	1			T12	717		T13	918		T15	129
valid_sources[0x59]	5841	1			T12	789		T13	820		T15	119
valid_sources[0x5a]	5023	1			T4	3		T6	1		T12	728
valid_sources[0x5b]	5940	1			T6	1		T12	764		T13	821
valid_sources[0x5c]	5144	1			T12	765		T13	895		T15	131
valid_sources[0x5d]	5454	1			T12	736		T13	869		T121	16
valid_sources[0x5e]	4550	1			T12	834		T13	861		T37	1
valid_sources[0x5f]	4853	1			T12	773		T16	2		T13	863
valid_sources[0x60]	4907	1			T12	805		T13	869		T15	138
valid_sources[0x61]	4965	1			T1	1		T12	846		T13	933
valid_sources[0x62]	4811	1			T12	743		T13	871		T15	104
valid_sources[0x63]	4999	1			T12	782		T13	867		T100	1
valid_sources[0x64]	4773	1			T12	802		T13	869		T36	3
valid_sources[0x65]	5629	1			T12	808		T13	898		T15	91
valid_sources[0x66]	4928	1			T12	755		T13	856		T64	1
valid_sources[0x67]	4891	1			T12	775		T16	1		T13	894
valid_sources[0x68]	5308	1			T12	763		T13	867		T15	127
valid_sources[0x69]	5249	1			T12	827		T13	860		T61	5
valid_sources[0x6a]	5093	1			T12	826		T13	857		T61	11
valid_sources[0x6b]	5595	1			T12	725		T13	931		T15	142
valid_sources[0x6c]	5088	1			T12	809		T13	883		T15	110
valid_sources[0x6d]	5160	1			T12	772		T16	2		T13	895
valid_sources[0x6e]	4924	1			T12	743		T13	881		T15	111
valid_sources[0x6f]	6313	1			T2	1		T12	853		T13	868
valid_sources[0x70]	5194	1			T12	794		T13	856		T15	134
valid_sources[0x71]	4727	1			T8	1		T12	740		T55	15
valid_sources[0x72]	5429	1			T1	1		T12	868		T13	876
valid_sources[0x73]	4843	1			T1	10		T4	3		T12	680
valid_sources[0x74]	4924	1			T12	722		T13	910		T15	121
valid_sources[0x75]	4980	1			T6	2		T12	710		T13	852
valid_sources[0x76]	5377	1			T12	753		T13	883		T15	122
valid_sources[0x77]	5563	1			T12	780		T13	831		T15	122
valid_sources[0x78]	5472	1			T6	2		T12	830		T13	829
valid_sources[0x79]	4779	1			T12	814		T13	813		T15	100
valid_sources[0x7a]	5599	1			T12	841		T13	848		T15	118
valid_sources[0x7b]	6015	1			T12	817		T13	858		T15	97
valid_sources[0x7c]	5116	1			T12	769		T13	918		T15	122
valid_sources[0x7d]	5771	1			T12	851		T13	877		T39	2
valid_sources[0x7e]	5279	1			T12	821		T13	853		T37	1
valid_sources[0x7f]	5241	1			T12	753		T13	867		T100	3
valid_sources[0x80]	5408	1			T12	818		T13	922		T15	115

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

308866

1

T1

12

T4

13

T6

9

values[0x0]

all_enables

biggest_size

463039

1

T10

1

T14

2

T12

68728

values[0x1]

all_enables

biggest_size

463069

1

T12

69114

T57

1

T13

76269