Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2945498

1

T3

110

T5

223

T6

22

full_word

1873721

1

T1

2

T3

12

T4

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4818909	1			T1	2		T3	122		T4	2
auto[TlIntgErrCmd]	86	1			T58	2		T59	4		T60	2
auto[TlIntgErrData]	102	1			T58	5		T59	10		T60	5
auto[TlIntgErrBoth]	122	1			T58	3		T59	6		T60	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

750347

1

T1

2

T3

122

T4

2

auto[1]

4068872

1

T12

623715

T13

706916

T15

93345

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	309363	1			T3	110		T5	223		T6	22
auto[TlIntgErrNone]	partial	auto[1]	2635850	1			T12	401357		T13	462302		T15	60131
auto[TlIntgErrNone]	full_word	auto[0]	440840	1			T1	2		T3	12		T4	2
auto[TlIntgErrNone]	full_word	auto[1]	1432856	1			T12	222358		T13	244614		T15	33214
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T58	1		T60	1		T104	4
auto[TlIntgErrCmd]	partial	auto[1]	42	1			T58	1		T59	3		T60	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T59	1		T105	1		T106	1
auto[TlIntgErrData]	partial	auto[0]	52	1			T58	2		T59	8		T60	2
auto[TlIntgErrData]	partial	auto[1]	41	1			T58	2		T59	2		T60	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T58	1		T60	1		T104	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T107	2		T108	1		T106	1
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T58	2		T60	2		T104	1
auto[TlIntgErrBoth]	partial	auto[1]	65	1			T58	1		T59	6		T60	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T109	1		T110	1		T111	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T108	1		T112	2		T113	1